ADSP-21991BST Analog Devices Inc, ADSP-21991BST Datasheet - Page 2

• Manufacturer Part Number: ADSP-21991BST
• Description: IC DSP CONTROLLER 16BIT 176LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21991BST

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP

ADSP-21991
KEY FEATURES (continued)
Integrated Power-On-Reset (POR) Generator
Flexible Power Management with Selectable Power-
2.5 V Internal Operation with 3.3 V I/O
Operating Temperature Range of –40ºC to +85ºC
196-Ball Mini-BGA Package
176-Lead LQFP Package
TARGET APPLICATIONS
Industrial Motor Drives
Uninterruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable Instrumentation
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 14
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Down and Idle Modes
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . 6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . 6
Serial Peripheral Interface (SPI) Port . . . . . . . . . . . . . 7
DSP Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . 7
Analog-to-Digital Conversion System . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PWM Generation Unit . . . . . . . . . . . . . . . . . . . . . . . 8
Auxiliary PWM Generation Unit . . . . . . . . . . . . . . . . 9
Encoder Interface Unit . . . . . . . . . . . . . . . . . . . . . . . 9
Flag I/O (FIO) Peripheral Unit . . . . . . . . . . . . . . . . 10
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . 10
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral Interrupt Controller . . . . . . . . . . . . . . . . 11
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset and Power-On Reset (POR) . . . . . . . . . . . . . . 12
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Set Description . . . . . . . . . . . . . . . . . . . 13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 13
Designing an Emulator-Compatible DSP Board . . . 14
Additional Information . . . . . . . . . . . . . . . . . . . . . . 14
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 22
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 5
External (Off-Chip) Memory . . . . . . . . . . . . . . . . . 5
External Memory Space . . . . . . . . . . . . . . . . . . . . . 5
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 6
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-Down Core Mode . . . . . . . . . . . . . . . . . . . 11
Power-Down Core/Peripherals Mode . . . . . . . . . . 12
Power-Down All Mode . . . . . . . . . . . . . . . . . . . . 12
–2–
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 41
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 42
GENERAL DESCRIPTION
The ADSP-21991 is a mixed signal DSP controller based on the
ADSP-219x DSP Core, suitable for a variety of high performance
industrial motor control and signal processing applications that
require the combination of a high performance DSP and the
mixed signal integration of embedded control peripherals such
as analog-to-digital conversion.
The ADSP-21991 integrates the fixed point ADSP-219x family
base architecture with a serial port, an SPI compatible port, a
DMA controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities, on-
chip program and data memory spaces, and a complete set of
embedded control peripherals that permits fast motor control
and signal processing in a highly integrated environment.
The ADSP-21991 architecture is code compatible with previous
ADSP-217x based ADMCxxx products. Although the architec-
tures are compatible, the ADSP-21991, with ADSP-219x
architecture, has a number of enhancements over earlier archi-
tectures. The enhancements to computational units, data address
generators, and program sequencer make the ADSP-21991 more
flexible and easier to program than the previous ADSP-21xx
embedded DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, twos complement value and base address registers for easier
implementation of circular buffering.
The ADSP-21991 integrates 40K words of on-chip memory con-
figured as 32K words (24-bit) of program RAM, and 8K words
(16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21991 operates with a 6.25 ns instruction cycle time for
a 160 MHz CCLK and with a 6.67 ns instruction cycle time for
a 150 MHz CCLK. All instructions, except two multiword
instructions, execute in a single DSP cycle.
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 22
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock In and Clock Out Cycle Timing . . . . . . . . . 23
Programmable Flags Cycle Timing . . . . . . . . . . . 24
Timer PWM_OUT Cycle Timing . . . . . . . . . . . . 25
External Port Write Cycle Timing . . . . . . . . . . . . 26
External Port Read Cycle Timing . . . . . . . . . . . . 27
External Port Bus Request/Grant Cycle Timing . . 28
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 29
Serial Peripheral Interface Port—Master Timing . 32
Serial Peripheral Interface Port—Slave Timing . . 33
JTAG Test And Emulation Port Timing . . . . . . . 34
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . 35
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 35
Example System Hold Time Calculation . . . . . . . 35
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