0W633-001-XTP ON Semiconductor, 0W633-001-XTP Datasheet - Page 21

• Manufacturer Part Number: 0W633-001-XTP
• Description: IC AUDIO PROCESSOR AD/DA 57LFBGA
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 250r
• Type: Floating Pointr

Specifications of 0W633-001-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 50MHz
• On-chip Ram: 42kB
• Voltage - I/o: 1.0V, 2.0V
• Voltage - Core: 1.00V, 2.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 57-LFBGA
• Package: 57CABGA
• Numeric And Arithmetic Format: Fixed-Point
• Ram Size: 16 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -

Analog Blocks
Input Stage
individual channels. For each channel, the selected one out
of the four possible inputs is routed to the input of the
programmable preamplifier that can be configured for
bypass or gain values of 12 to 30 dB (3 dB steps).
20 kHz before it is passed into the high−fidelity 16−bit
oversampling SD A/D converter. Subsequently, any
necessary sample rate decimation is performed to
downsample the signal to the desired sampling rate. During
decimation the level of the signal can be adjusted digitally
for optimal gain matching between the two input channels.
Any undesired DC component can be removed by a
Table 10. INTERRUPT DESCRIPTIONS
WOLA_DONE
IO_BLOCK_FULL
GP_TIMER
WATCHDOG_TIMER
SPI_INTERFACE
IR
EXT3_RX
EXT3_TX
GPIO
TWSS_INTERFACE
UART_RX
UART_TX
PCM
The analog audio input stage is comprised of two
The analog signal is filtered to remove frequencies above
Interrupt
WOLA function done
IOP interrupt
General−purpose timer interrupt
Watchdog timer interrupt
SPI interface interrupt
IR remote interrupt
EXT3 register receive interrupt
EXT3 register transmit interrupt
User configurable GPIO interrupt
Two−wire synchronous serial interface interrupt
General−purpose UART receive interrupt
General−purpose UART transmit interrupt
PCM interface interrupt
Figure 7. Input Stage
Description
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configurable DC−removal filter that is part of the
decimation circuitry. The DC removal filter can be
configured for bypass or cut−off frequencies at 5, 10 and
20 Hz.
configured between channel zero and channel one (or vice
versa). This is useful in beam−forming applications.
Note: Both preamplifiers can be daisy−chained to increase
the potential gain, but the signal has to be routed externally
to the chip.
channels can be disabled via software. A different input
must be selected for each channel. The input stage is shown
in Figure 7.
A built−in feature allows a sampling delay to be
For power consumption savings either of the input