0W633-001-XTP ON Semiconductor, 0W633-001-XTP Datasheet - Page 20

• Manufacturer Part Number: 0W633-001-XTP
• Description: IC AUDIO PROCESSOR AD/DA 57LFBGA
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 250r
• Type: Floating Pointr

Specifications of 0W633-001-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 50MHz
• On-chip Ram: 42kB
• Voltage - I/o: 1.0V, 2.0V
• Voltage - Core: 1.00V, 2.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 57-LFBGA
• Package: 57CABGA
• Numeric And Arithmetic Format: Fixed-Point
• Ram Size: 16 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -

Memory Maps
General−Purpose Timer
with a 3−bit prescaler that interrupts the RCore when it
reaches zero. It can operate in two modes, single−shot or
continuous. In single−shot mode, the timer counts down
only once and then generates an interrupt. It will then have
to be restarted from the RCore. In continuous mode, the
timer “wraps around” every time it hits zero and interrupts
are generated continuously. This unit is often useful in
scheduling tasks that are not part of the sample−based
signal−processing scheme, such as checking a battery
voltage or reading the value of a volume control.
Complete memory maps for BelaSigna 250 are shown in Figure 6.
The general−purpose timer is a 12−bit countdown timer
X:0xFFFF
X:0x1B7F
X:0x0FFF
X:0x423F
X:0x417F
X:0x407F
X:0x207F
X:0x1A00
X:0x197F
X:0x13FF
X:0x12FF
X:0x10FF
X:0x4180
X:0x4080
X:0x4000
X:0x2000
X:0x1800
X:0x1300
X:0x1200
X:0x11FF
X:0x1000
X:0x0000
X:0x1100
Mirrored Temp. Memory
Mirrored Temp. Memory
Mirrored Temp. Memory
Mirrored Temp. Memory
Smart Input FIFO
X Data RAM
(4096 x 16)
Input FIFO
Microcode
X Memory
(192 x 16)
(256 x 16)
(128 x 16)
ROM LUT
(128 x 16)
(384 x 16)
(384 x 16)
(256 x 18)
(256 x 18)
(256 x 18)
(256 x 18)
Window
Gain
Shifted by N_FFT
Access bits (17:2)
Access bits (16:1)
Access bits (15:0)
Figure 6. Memory Maps
Y:0xFFFF
Y:0x1B7F
Y:0x1A00
Y:0x0FFF
Y:0x404F
Y:0x403F
Y:0x197F
Y:0x8012
Y:0x8000
Y:0x4010
Y:0x4000
Y:0x1800
Y:0x0000
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Digital Control Registers
Configuration Registers
Control Register and
Smart Output FIFO
Watchdog Timer
that operates from the system clock and is used to ensure
system sanity. It is always active and must be periodically
acknowledged as a check that an application is still running.
Once the watchdog times out, it generates an interrupt. If left
to time out a second consecutive time without
acknowledgement, BelaSigna 250 will fully reset itself.
Interrupts
interrupt sources in a prioritized manner. The interrupt
controller also handles interrupt acknowledge flags. Every
interrupt source has its own interrupt vector. Furthermore,
the priority scheme of the interrupt sources can be modified.
Refer to Table 10 for a description of all interrupts.
Output FIFO
Y Data RAM
The watchdog timer is a programmable hardware timer
The RCore has a single interrupt channel that serves 13
(4096 x 16)
Data Buffer
Y Memory
(384 x 16)
(384 x 16)
(19 x 16)
(17 x 16)
(17 x 16)
P:0xFFFF
P:0x3FFF
P:0x3FF0
P:0x03FF
P:0x1000
P:0x0000
Interrupt Vectors
Program ROM
Program RAM
(12288 x 16)
(1024 x 16)
P Memory
(16 x 16)