Z8937320FSG Zilog, Z8937320FSG Datasheet - Page 25

• Manufacturer Part Number: Z8937320FSG
• Description: DSP 20MHZ 80-PQFP
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8937320FSG

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ZiLOG
Interrupts.
which can be programmed to be positive or negative edge-
triggered. There are five interrupts generated by internal pe-
ripherals: the A/D converter, the Serial Peripheral Interface,
and the three Counter/Timers. Internally there are three pri-
ority levels. The internal signals for Interrupt service Re-
quests are denoted ISR0, ISR1, and ISR2, with ISR0 having
the highest priority, and ISR2 the lowest. The user can pro-
gram which interrupt sources are enabled, and which sourc-
es are serviced by the highest, middle, and lowest priority
service routines. An interrupt is serviced at the end of an
instruction execution. Two machine cycles are required to
enter an interrupt instruction sequence. The PC is pushed
onto the stack. The Interrupt Controller fetches the address
of the interrupt service routine from the following locations
in program memory:
At the end of the interrupt service routine, a RET instruction
is used to pop the stack into the PC.
The Set-Interrupt-Enable-Flag (SIEF) instruction enables
the interrupts. Interrupts are automatically disabled when
entering an interrupt service routine. Before exiting an in-
terrupt service routine the SIEF instruction can be used to
reenable interrupts.
Registers.
ing, control, and configuration, the Z893x3 offers up to sev-
en user-defined 16-bit external registers, EXT0–EXT6, de-
pending on the Register Bank Select value. The external
register address space is shared by the Z893x3 internal pe-
ripherals. Selecting banks 0–4 of the EXT Register Assign-
ment allows access to/from three to seven of these addresses
for general-purpose use.
I/O Ports.
urable I/O structure. Most of the I/O pins include dual func-
tions. The Counter/Timer, Serial Peripheral Interface, and
External Interrupt Enables determine whether a pin is ded-
icated to peripheral or I/O port use.
Port0.
put or output or globally as open-drain output. When en-
abled, Port0 consumes the 16 data lines used by the ED bus.
Port0 function and ED bus use can be dynamically alter-
nated by enabling and disabling Port0.
Port1.
as input or output or globally as open-drain output. Port1
also supports INT2, CLKOUT, the Serial Peripheral Inter-
face, and User Inputs 0 and 1.
DS000202-DSP0599
Device
Z89223/273/323/373
A 16-bit user I/O port. Bits can be configured as in-
A multifunctional 8-bit port. Bits can be configured
The Z893X3 DSP family features a user-config-
In addition to the internal registers for process-
The Z893x3 features three user interrupt inputs
ISR0
1FFFH
ISR1
1FFEH
ISR2
1FFDH
Port2.
as input or output or globally as open-drain output. Port2
also supports INT0 and INT1, all three Counter/Timer out-
puts, ED Bus, WAIT, and UI2.
Port3.
4 bits of output. It is available only on the 80-pin package.
External Register Usage.
EXT0–EXT6 are accessed using the External Address Bus
EA2–EA0, the External Data Bus (ED Bus) ED15–ED0,
and control signals DS, WAIT, and RD/WR. These provide
a convenient data transfer capability with external periph-
erals. Data transfers can be performed in a single-cycle. An
internal wait state generator is provided to accommodate
slower external peripherals. A single wait state can be im-
plemented through control register Bank15/EXT3. For ad-
ditional wait states, the WAIT pin can be used. The WAIT
pin is monitored only during execution of a read or write
instruction to external peripherals on the ED bus.
Wait-State Generator.
is provided to accommodate slow external peripherals. A
single Wait-State can be implemented through a control
register. For additional states, a dedicated pin (WAIT) can
be held Low. The WAIT pin is monitored only during ex-
ecution of a read or write instruction to external peripherals
(ED bus).
Analog to Digital Converter.
channel, 8-bit half-flash converter. Two external reference
voltages provide a scalable input range. The A/D sample
rate is determined by a prescaler connected to the system
clock. An interrupt is optionally generated at the end of a
conversion. The four input channels can be programmed to
operate on demand, continuously, or upon an event (timer
or interrupt).
Counter/Timers (C/T0 and C/T1).
with 8-bit prescalers. They also offer the option of being
used as PWM generators and include both hardware and
software Watch-Dog capabilities. Both C/Ts are identical
and can be externally or internally clocked. Either C/T can
drive TMO0 or TMO1. Either C/T can drive any of the three
interrupt service requests (ISR0, ISR1, or ISR2).
Counter/Timer (C/T2).
internally clocked, and can drive TMO2 and/or any of the
three interrupt service requests (ISR0, ISR1, or ISR2).
Serial Peripheral Interface (SPI).
Interface provides a convenient means of inter-processor
and processor-peripheral communication. It offers the ca-
pability to transmit and receive simultaneously. The SPI is
designed to operate in either master or slave mode.
16-Bit Digital Signal Processors with A/D Converter
A multifunctional 8-bit port. Bits can be configured
Port3 is an 8-bit user I/O port with 4 bits of input and
An internal Wait-State generator
This C/T is 16-bits, externally or
T h e e x t e r n a l r e g i s t e r s
The A/D Converter is a 4-
The Serial Peripheral
These C/Ts are 16-bit
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