ADSP-21061KS-133 Analog Devices Inc, ADSP-21061KS-133 Datasheet - Page 37

• Manufacturer Part Number: ADSP-21061KS-133
• Description: IC DSP CONTROLLER 32BIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061KS-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Frequency: 33MHz
• Supply Voltage: 5V
• Embedded Interface Type: HPI, Serial
• No. Of Mips: 50
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes, DMARx is used to initiate transfers. For
Handshake mode, DMAGx controls the latching or enabling of
data externally. For External Handshake mode, the data transfer
is controlled by the ADDR31–0, RD, WR, SW, PAGE, MS3–0,
Table 20. DMA Handshake
1
2
3
4
5
6
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
Only required for recognition in the current cycle.
t
For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min.
t
See
For the ADSP-21061L (3.3 V), this specification is –1.0 ns min.
SDATDGL
VDATDGH
SDRLC
SDRHC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
VDATDGH
DATRDGH
DGWRL
DGWRH
DGWRR
DGRDL
DRDGH
DGRDR
DGWR
DADGH
DDGHA
be driven t
the number of extra cycles that the access is prolonged.
Example System Hold Time Calculation on Page 44
CK
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
DATDRH
DMARx Low Setup Before CLKIN
DMARx High Setup Before CLKIN
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low
Data Hold After DMAGx High
Data Valid After DMARx High
DMARx Low Edge to Low Edge
DMARx Width High
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High
Data Disable After DMAGx High
WR Low Before DMAGx Low
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
Address/Select Hold after DMAGx High
after DMARx is brought high.
2
2
3
4
5
1
1
for calculation of hold times given capacitive and dc loads.
6
Rev. C | Page 37 of 56 | July 2007
t
CK
.
ACK, and DMAGx signals. For Paced Master mode, the data
transfer is controlled by ADDR31–0, RD, WR, MS3–0, and
ACK (not DMAG). For Paced Master mode, the Memory Read-
Bus Master, Memory Write-Bus Master, and Synchronous
Read/Write-Bus Master timing specifications for ADDR31–0,
RD, WR, MS3–0, SW, PAGE, DATA47–0, and ACK also apply.
Min
5
5
6
2
23 + 7DT/8
6
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
0
10 + 5DT/8 +W
1 + DT/16
0
11 + 9DT/16 + W
0
5 + 3DT/8 + HI
17 + DT
–0.5
ADSP-21061/ADSP-21061L
VDATDGH
= t
5 V and 3.3 V
CK
– .25t
CCLK
Max
10 + 5DT/8
16 + 7DT/8
15 + DT/4
6 – DT/8
7
2
3 + DT/16
2
3
– 8 + (n × t
CK
) where n equals
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns