ADSP-2196MKSTZ-160 Analog Devices Inc, ADSP-2196MKSTZ-160 Datasheet - Page 51

• Manufacturer Part Number: ADSP-2196MKSTZ-160
• Description: IC DSP CONTROLLER 16BIT 144-LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2196MKSTZ-160

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 160MHz
• Non-volatile Memory: ROM (48 kB)
• On-chip Ram: 40kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 160MHz
• Mips: 160
• Device Input Clock Speed: 160MHz
• Ram Size: 40KB
• Program Memory Size: 48KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 22. JTAG Port Timing
1
2
3
REV. PrA
System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,
TFS0, TFS1, RFS0, RFS1, BMS.
System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,
CLKIN, RESET.
50 MHz max.
September 2001
Parameter
Switching Characteristics
t
t
Timing Parameters
t
t
t
t
t
t
DTDO
DSYS
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
Description
TDO Delay from TCK Low
System Outputs Delay After TCK Low
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at 800/262-5643
3
Figure 26. JTAG Port Timing
2
2
1
JTAG Test And Emulation Port Timing
Table 22
and
Figure 26
Min
0
20
4
describe JTAG port operations.
Max
4
5
4
4
4
5
ADSP-2196
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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