ADSP-2191MKSTZ-160 Analog Devices Inc, ADSP-2191MKSTZ-160 Datasheet - Page 22

• Manufacturer Part Number: ADSP-2191MKSTZ-160
• Description: IC DSP CONTROLLER 16BIT 144LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2191MKSTZ-160

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 16 Bit
• Frequency: 160MHz
• Supply Voltage: 3.3V
• Embedded Interface Type: HPI, SPI, UART
• No. Of I/o's: 16
• No. Of Mips: 160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-2191M
External Port Write Cycle Timing
Table 12
The external port lets systems extend read/write accesses in three
ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising
Table 12. External Port Write Cycle Timing
1
2
3
4
t
These are timing parameters that are based on worst-case operating conditions.
W = (number of waitstates specified in wait register)
Write hold cycle–memory select control registers (MS
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
Timing Requirements
t
t
HCLK
CSWS
AWS
WSCS
WSA
WW
CDA
CDD
DSW
DHW
DHW
WWR
AKW
DWSAK
is the peripheral clock period.
and
1, 2
Figure 11
M S 3 – 0
A 2 1 – 0
D 1 5 – 0
IO M S
B M S
A C K
W R
R D
Chip Select Asserted to WR Asserted Delay
Address Valid to WR Setup and Delay
WR Deasserted to Chip Select Deasserted
WR Deasserted to Address Invalid
WR Strobe Pulsewidth
WR to Data Enable Access Delay
WR to Data Disable Access Delay
Data Valid to WR Deasserted Setup
WR Deasserted to Data Invalid Hold Time; E_WHC
WR Deasserted to Data Invalid Hold Time; E_WHC
WR Deasserted to WR, RD Asserted
ACK Strobe Pulsewidth
ACK Delay from WR Low
describe external port write operations.
t
A W S
t
t
D W S A K
C S W S
t
C D A
Figure 11. External Port Write Cycle Timing
t
HCLK.
CTL).
t
A K W
t
W W
–22–
edge of EMI clock. ACK low causes the DSP to wait, and the
DSP requires two EMI clock cycles after ACK goes high to finish
the access. For more information, see the External Port chapter
in the ADSP-219x/ADSP-2191 DSP Hardware Reference.
t
D S W
4
4
Min
0.5t
0.5t
0.5t
0.5t
t
0.5t
t
3.4
t
t
12.5
0
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
–2+W
+1+W
+3.4
–4
–3
–4
–3
–3
t
t
D H W
C D D
t
t
t
W S C S
W S A
W W R
3
3
Max
0
0.5t
t
HCLK
HCLK
+7+W
+4
3
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns