EPM9560ARI208-10 Altera, EPM9560ARI208-10 Datasheet - Page 16

IC MAX 9000 CPLD 560 208-RQFP

EPM9560ARI208-10

Manufacturer Part Number
EPM9560ARI208-10
Description
IC MAX 9000 CPLD 560 208-RQFP
Manufacturer
Altera
Series
MAX® 9000r
Datasheet

Specifications of EPM9560ARI208-10

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
35
Number Of Macrocells
560
Number Of Gates
12000
Number Of I /o
153
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-RQFP
Voltage
3.3V/5V
Memory Type
EEPROM
Number Of Logic Elements/cells
35
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2364

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MAX 9000 Programmable Logic Device Family Data Sheet
16
Figure 9. MAX 9000 Column-to-IOC Connections
Dedicated Inputs
In addition to the general-purpose I/O pins, MAX 9000 devices have four
dedicated input pins. These dedicated inputs provide low-skew, device-
wide signal distribution to the LABs and IOCs in the device, and are
typically used for global clock, clear, and output enable control signals.
The global control signals can feed the macrocell or IOC clock and clear
inputs, as well as the IOC output enable. The dedicated inputs can also be
used as general-purpose data inputs because they can feed the row
FastTrack Interconnect (see
I/O Cells
Figure 10
device from either the I/O pins that provide general-purpose input
capability or from the four dedicated inputs. The IOCs are located at the
ends of the row and column interconnect channels.
Each IOC is driven by
a 17-to-1 multiplexer.
shows the IOC block diagram. Signals enter the MAX 9000
IOC1
17
Figure 2 on page
Column FastTrack
Interconnect
48
48
48
IOC10
17
7).
Altera Corporation
Each IOC can drive up
to two column
channels.

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