EPM9560ARI240-10 Altera, EPM9560ARI240-10 Datasheet - Page 17

• Manufacturer Part Number: EPM9560ARI240-10
• Description: IC MAX 9000 CPLD 560 240-RQFP
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9560ARI240-10

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 35
• Number Of Macrocells: 560
• Number Of Gates: 12000
• Number Of I /o: 191
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-RQFP
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 35
• Family Name: MAX 9000
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 144.9MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 191
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2365

Altera Corporation
Figure 10. MAX 9000 IOC
I/O pins can be used as input, output, or bidirectional pins. Each IOC has
an IOC register with a clock enable input. This register can be used either
as an input register for external data that requires fast setup times, or as an
output register for data that requires fast clock-to-output performance.
The IOC register clock enable allows the global clock to be used for fast
clock-to-output performance, while maintaining the flexibility required
for selective clocking.
The clock, clock enable, clear, and output enable controls for the IOCs are
provided by a network of I/O control signals. These signals can be
supplied by either the dedicated input pins or internal logic. The IOC
control-signal paths are designed to minimize the skew across the device.
All control-signal sources are buffered onto high-speed drivers that drive
the signals around the periphery of the device. This “peripheral bus” can
be configured to provide up to eight output enable signals, up to four
clock signals, up to six clock enable signals, and up to two clear signals.
Table 6 on page 18
how the IOC control signals share the peripheral bus.
To Row or
Column FastTrack
Interconnect
From Row or
Column FastTrack
Interconnect
Peripheral Control
Bus [12..0]
MAX 9000 Programmable Logic Device Family Data Sheet
13
OE [7..0]
CLK [3..0]
ENA [5..0]
CLR [1..0]
shows the sources that drive the peripheral bus and
8
4
6
2
VCC
VCC
VCC
D
ENA
CLRN
Q
Slew-Rate
Control
17