EPM3256AQC208-10N Altera, EPM3256AQC208-10N Datasheet - Page 10

IC MAX 3000A CPLD 256 208-PQFP

EPM3256AQC208-10N

Manufacturer Part Number
EPM3256AQC208-10N
Description
IC MAX 3000A CPLD 256 208-PQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet

Specifications of EPM3256AQC208-10N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
158
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 3000A
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
16
# I/os (max)
158
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1988
EPM3256AQC208-10N

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MAX 3000A Programmable Logic Device Family Data Sheet
Figure 4. MAX 3000A Parallel Expanders
10
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
36 Signals
from PIA
Expanders
16 Shared
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB.
into the LAB. An EEPROM cell controls one input to a two-input AND gate,
which selects a PIA signal to drive into the LAB.
Product-
Product-
Select
Matrix
Select
Matrix
Ter
T T m
er
Macrocell
Previous
From
Figure 5
shows how the PIA signals are routed
Macrocell
To Next
Preset
Clock
Clear
Preset
Clock
Clear
Altera Corporation
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic

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