AD9709AST Analog Devices Inc, AD9709AST Datasheet - Page 14

• Manufacturer Part Number: AD9709AST
• Description: IC DAC 8BIT DUAL 125MSPS 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9709AST

• Rohs Status: RoHS non-compliant
• Settling Time: 35ns
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 450mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: AD9709-EBZ - BOARD EVAL FOR AD9709

AD9709
DAC TRANSFER FUNCTION
Both DACs in the AD9709 provide complementary current out-
puts, I
output, I
while I
The current output appearing at I
both the input code and I
where DAC CODE = 0 to 255 (that is, decimal representation).
I
nominally set by a reference voltage (V
resistor (R
where
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, I
should be connected directly to matching resistive loads, R
that are tied to the analog common, ACOM. Note that R
can represent the equivalent load resistance seen by I
I
cable. The single-ended voltage output appearing at the I
and I
Note the full-scale value of V
specified output compliance range to maintain the specified
distortion and linearity performance.
Equation 7 highlights some of the advantages of operating the
AD9709 differentially. First, the differential operation helps cancel
common-mode error sources associated with I
such as noise, distortion, and dc offsets. Second, the differential
code-dependent current and subsequent voltage, V
the value of the single-ended voltage output (that is, V
V
Note that the gain drift temperature performance for a single-
ended (V
AD9709 can be enhanced by selecting temperature tracking
resistors for R
ANALOG OUTPUTS
The complementary current outputs, I
DAC can be configured for single-ended or differential
operation. I
single-ended voltage outputs, V
resistor, R
The differential voltage, V
can be converted to a single-ended voltage via a transformer or
OUTFS
OUTB
OUTB
I
I
I
I
, as would be the case in a doubly terminated 50 Ω or 75 Ω
V
V
V
OUTB
OUTA
OUTB
OUTFS
REF
), thus providing twice the signal power to the load.
is a function of the reference current (I
OUTA
OUTA
OUTB
DIFF
OUTB
OUTFS
= V
OUTA
nodes is
= (255 − DAC CODE)/256 × I
LOAD
= (DAC CODE/256) × I
= (I
SET
= 32 × I
and I
, the complementary output, provides no current.
= I
= I
OUTA
REFIO
). It can be expressed as
, when all bits are high (that is, DAC CODE = 256)
OUTA
OUTB
OUTA
, as described in Equation 5 through Equation 7.
and V
LOAD
OUTB
/R
and I
× R
× R
− I
and R
REF
SET
. I
OUTB
OUTB
OUTB
LOAD
OUTA
LOAD
) or differential output (V
OUTFS
SET
) × R
can be converted into complementary
DIFF
provides a near full-scale current
due to their ratiometric relationship.
and can be expressed as
OUTA
, existing between V
LOAD
OUTA
OUTA
and V
OUTFS
and V
and I
OUTA
REFIO
OUTB
OUTFS
OUTB
) and an external
and I
OUTB
must not exceed the
REF
, via a load
OUTA
), which is
is a function of
OUTA
OUTB
OUTA
DIFF
DIFF
and I
, in each
and I
) of the
OUTA
and V
, is twice
OUTA
LOAD
OUTB
OUTA
or
OUTB
LOAD
or
OUTB
,
Rev. B | Page 14 of 32
(1)
(2)
(3)
(4)
(5)
(6)
(7)
,
differential amplifier configuration. The ac performance of the
AD9709 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at I
and I
is desirable, I
The distortion and noise performance of the AD9709 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I
significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases. This is due to the first-order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (that is, assuming no
source termination). Because the output currents of I
I
differentially. A properly selected transformer allows the AD9709
to provide the required power and voltage levels to different loads.
The output impedance of I
equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V
device. As a result, maintaining I
ground via an I-V op amp configuration results in the optimum
dc linearity. Note that the INL/DNL specifications for the
AD9709 are measured with I
via an op amp.
I
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a
breakdown of the output stage and affect the reliability of the
AD9709.
The positive output compliance range is slightly dependent on
the full-scale output current, I
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at I
does not exceed 0.5 V. Applications requiring the AD9709 output
(that is, V
should size R
range adversely affects the linearity performance of the AD9709
and subsequently degrade its distortion performance.
OUTB
OUTA
OUTB
are complementary, they become additive when processed
and I
OUTA
is limited to ±0.5 V. If a single-ended unipolar output
OUTB
LOAD
OUTA
and/or V
also have a negative and positive voltage
accordingly. Operation beyond this compliance
should be selected.
OUTA
and V
OUTB
) to extend its output compliance range
OUTA
OUTB
OUTA
OUTFS
and I
) due to the nature of a PMOS
OUTA
maintained at a virtual ground
. When I
OUTB
and/or I
OUTA
is determined by the
and I
OUTFS
OUTB
OUTB
is decreased
OUTA
at a virtual
can be
OUTA
and I
and
OUTB
OUTA