AD9709-EBZ Analog Devices Inc, AD9709-EBZ Datasheet
AD9709-EBZ
Specifications of AD9709-EBZ
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AD9709-EBZ Summary of contents
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... DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9709 to interface to two separate data ports single interleaved high speed data port. In inter- leaving mode, the input data stream is demuxed into its original I and Q data and then latched ...
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... Analog Outputs .......................................................................... 14 Digital Inputs .............................................................................. 15 DAC Timing ................................................................................ 15 Sleep Mode Operation ............................................................... 18 Power Dissipation....................................................................... 18 Applying the AD9709 .................................................................... 19 Output Configurations .............................................................. 19 Differential Coupling Using a Transformer ............................ 19 Differential Coupling Using an Op Amp ................................ 19 Single-Ended, Unbuffered Voltage Output ............................. 20 Single-Ended, Buffered Voltage Output Configuration ........ 20 ...
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... V 100 kΩ 1.20 1.26 V 100 nA 1. MΩ 0.5 MHz 0 ppm of FSR/°C ±50 ppm of FSR/°C ±100 ppm of FSR/°C ±50 ppm/° 380 410 mW 420 450 mW 450 mW +0 FSR/V +0.025 % of FSR/V +85 °C = 100 MSPS, and MHz. OUT AD9709 ...
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... AD9709 DYNAMIC SPECIFICATIONS AVDD = 3 DVDD1 = DVDD2 = 3 MIN MAX doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLK 1 Output Settling Time ( 0.1% ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) 1 Output Noise (I ...
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... OUTFS Min 3.5 2.1 0 −10 −10 2.0 1.5 3 DATA IN t LPW t CPW I OUTA OR I OUTB t PD Figure 2. Timing for Dual and Interleaved Modes Rev Page AD9709 Typ Max Unit 1.3 V 0.9 V +10 μA +10 μ ...
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... AD9709 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To AVDD ACOM DVDD1, DVDD2 DCOM1/DCOM2 ACOM DCOM1/DCOM2 AVDD DVDD1/DVDD2 MODE, CLK1/IQCLK, DCOM1/DCOM2 CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL Digital Inputs DCOM1/DCOM2 ACOM OUTA1 OUTA2 I /I OUTB1 OUTB2 REFIO, FSADJ1, ACOM FSADJ2 GAINCTRL, SLEEP ACOM Junction Temperature ...
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... Full-Scale Current Output Adjust for DAC2 Master/Slave Resistor Control Mode. Reference Input/Output Full-Scale Current Output Adjust for DAC1 Port 1 Differential DAC Current Outputs Analog Supply Voltage Mode Select (1 = dual port interleaved) Rev Page DB0P2 (LSB) 30 DB1P2 29 DB2P2 28 DB3P2 27 DB4P2 26 DB5P2 25 AD9709 ...
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... AD9709 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3 DVDD = 3 unless otherwise noted 5MSPS CLK 65MSPS 55 CLK f = 125MSPS CLK (MHz) OUT Figure 4. SFDR vs dBFS OUT 75 70 0dBFS 65 –6dBFS 60 –12dBFS 0.5 1.0 1.5 f (MHz) OUT Figure 5. SFDR vs MSPS OUT 75 70 0dBFS 65 –6dBFS 60 55 –12dBFS 50 45 ...
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... CLK 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 –0.01 – CLK Rev Page AD9709 I = 20mA OUTFS I = 5mA OUTFS I = 10mA OUTFS 100 120 f (MSPS) CLK and MHz and 0 dBFS CLK OUTFS OUT 128 ...
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... AD9709 10MHz OUT 25MHz OUT 40MHz OUT 60MHz OUT 50 45 –50 –30 – TEMPERATURE (°C) Figure 16. SFDR vs. Temperature @ f CLK 0.05 0.03 OFFSET ERROR 0 –0.03 –0.05 –40 – TEMPERATURE (°C) Figure 17. Gain and Offset Error vs. Temperature @ f 0 –10 –20 –30 –40 –50 – ...
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... Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal expressed as a percentage or in decibels (dB). Rev Page AD9709 For offset MIN MAX ...
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... WRT1/ GAINCTRL IQWRT DVDD1/DVDD2 50Ω DCOM1/DCOM2 RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2 R 1 SET 2kΩ FSADJ1 I 1 REF 0.1µF ...
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... I REF 22nF R SET Figure 24. External Reference Configuration GAIN CONTROL MODE The AD9709 allows the gain of each channel to be set independently by connecting one R another R system cost, a single R both channels simultaneously. When GAINCTRL is low (that is, connected to analog ground), . the independent channel gain control mode using two resistors is enabled ...
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... DIFF from mA, the positive output compliance range degrades slightly from its nominal 1. 1.00 V. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at I does not exceed 0.5 V. Applications requiring the AD9709 output and each OUTB (that is, V ...
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... IQRESET Figure 25. Latch Structure in Interleaved Mode Dual Port Mode Timing When the MODE pin is at Logic 1, the AD9709 operates in dual port mode (refer to Figure 21). The AD9709 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines. ...
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... AD9709 remains enabled if this input is left disconnected. Because the AD9709 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9709 ...
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... The AD9709 is rising-edge triggered and therefore exhibits SNR sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9709 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 32 shows the relationship of SNR to clock/data placement ...
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... AD9709 SLEEP MODE OPERATION The AD9709 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 3 and temperature range. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 × ...
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... The differential circuit shown in Figure 38 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9709 and the op amp, is used to level shift the differential output of the AD9709 to midsupply (that is, AVDD/2). The AD8041 ...
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... DAC’s full-scale current common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum from tens of kilohertz to several megahertz. The PSRR vs. frequency of the AD9709 AVDD supply over this frequency range is shown in Figure 41. ( OUTA ...
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... IN Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9709 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, decouple the analog supply (AVDD) to the analog common (ACOM) as close to the chip as physically possible ...
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... I and Q channels, and it shows a path for upconversion using the AD8346 quadrature modulator. The AD9709 provides both I and Q DACs with a common reference that will improve the gain matching and stability. R used to compensate for any mismatch in gain between the two channels ...
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... I and Q digital data can be fed into the AD9709 in two ways. In dual port mode, the digital I information drives one input port, and the digital Q information drives the other input port interpolation filter precedes the DAC, the symbol rate is the rate at which the system clock drives the CLK and WRT pins on the AD9709 ...
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... INCK2 10 Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board (1) This board allows the user flexibility to operate the AD9709 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single-ended and differential outputs. The digital inputs can be used in dual port or interleaved mode and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination ...
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... CC0805 CC0805 Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2) Rev Page RC0603 RC0805 RC0805 RC0805 RC0805 RC0805 AD9709 00606-147 ...
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... C30 2 C26 100PF C25 100PF DNP R26 51 C32 RC0603 DNP JP20 CC0805 DNP R25 51 R24 RC0603 Figure 48. Modulator on AD9709 Evaluation Board Rev Page DNP DNP RC0603 MODULATED OUTPUT AGND2;3,4,5 R27 0 SMAEDGE C28 J1 RC0603 100PF AVDD2 2 TP6 RED AVDD2 R28 1K AGND2 TP5 ...
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... RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 49. Digital Input Signaling (1) Rev Page AD9709 00606-149 ...
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... AD9709 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 50. Digital Input Signaling (2) Rev Page 00606-150 ...
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... CC0805 CC0805 RC07CUP RC0805 RC0805 Figure 51. Device Under Test/Analog Output Signal Conditioning Rev Page RC07CUP RC0805 RC0805 AD9709 00606-151 ...
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... AD9709 EVALUATION BOARD LAYOUT Figure 52. Assembly, Top Side Rev Page ...
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... Figure 53. Assembly, Bottom Side Rev Page AD9709 ...
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... ORDERING GUIDE Model Temperature Range AD9709ASTZ 1 –40°C to +85°C 1 AD9709ASTZRL –40°C to +85°C 1 AD9709-EBZ RoHS Compliant Part. ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.75 1.60 0.60 MAX 0.45 ...