K4H281638B-TCB0000 Samsung Semiconductor, K4H281638B-TCB0000 Datasheet

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... DDR SDRAM DDR SDRAM Specification Version 1. REV. 1.31 Nov. 3. 2001 ...

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... Added QFC Function. - Added DC current value - Reduce I/O capacitance values Version 0.4(Feb,1999) -Added DDR SDRAM history for reference(refer to the following page) -Added low power version DC spec Version 0.5(Apr,1999) -Revised following first showing for JEDEC standard -Added DC target current based on new DC test condition Version 0 ...

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... Changed DC spec item & test condition Version 0.73(June,2000) - Added updated DC spec values - Deleted tDAL in AC parameter Version 1.0(July,2000) - Eliminate "preliminary" to K4H280438B-TC(L)A2/B0/A0 K4H280838B-TC(L)A2/B0/A0 K4H281638B-TC(L)A2/B0/A0 to 2.0pF ~ 3.0pF w/ Delta Cin = 0.25pF 4.0pF ~ 5.0pF w/ Delta Cin = 0.5pF 2.0pF ~ 3.0pF with Delta Cin = 0.5pF to Vref +/- 0.31V Vref +/- 0.15V 3ns at VDD. ...

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... DDR SDRAM Version 1.1(February,2001) - Updated DC current value. - Changed V (DC), Input differential voltage, CK and CK inputs min. from 0.3V to 0.36V Added V (DC), Input crossing point voltage, CK and CK inputs to 1.15V ~1.35V Added Output high/low current Added Pullup current to pulldown current ratio to 0.71 ~ 1.4. ...

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... DDR SDRAM Version 1.3(October,2001) - Modificated typo. - Changed pin # 17 from NC to A13 in Package pinout. - Revised "Write with autoprecharge" table in page 29. - Added tIS and tPDEX parameters in "power down" timing of page 31. - Revised "Absolute maximum rating" table in page 38. . Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V . Changed " ...

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... No Operation(NOP) & Device Deselect 3.2.5 Row Active 3.2.6 Read Bank 3.2.7 Write Bank 3.3 Essential Functionality for DDR SDRAM 3.3.1 Burst Read Operation 3.3.2 Burst Write Operation 3.3.3 Read Interrupted by a Read 3.3.4 Read Interrupted by a Write & Burst Stop 3 ...

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... DDR SDRAM 3.3.7 Write Interrupted by a Read & DM 3.3.8 Write Interrupted by a Precharge & DM 3.3.9 Burst Stop 3.3.10 DM masking 3.3.11 Read With Auto Precharge 3.3.12 Write With Auto Precharge 3.3.13 Auto Refresh & Self Refresh 3.3.14 Power Down 4. Command Truth Table 5 ...

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... DDR SDRAM List of tables Table 1 : Operating frequency and DLL jitter Table 2. : Column address configurtion Table 3 : Input/Output function description Table 4 : Burst address ordering for burst length Table 5 : Bank selection for precharge by bank address bits Table 6 : Operating description when new command asserted while ...

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... DDR SDRAM List of figures Figure 1 : 128Mb Package Pinout Figure 2 : Package dimension Figure 3 : State digram Figure 4 : Power up and initialization sequence Figure 5 : Mode register set Figure 6 : Mode register set sequence Figure 7 : Extend mode register set Figure 8 : Bank activation command cycle timing Figure 9 : Burst read operation timing ...

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... D : 5th Generation E : 6th Generation 9. Package T : TSOP2 (400mil x 875mil) 10. Temperature & Power C : (Commercial, Normal (Commercial, Low) 11. Speed A0 : 10ns@CL2 A2 : 7.5ns@CL2 B0 : 7.5ns@CL2 100Mhz w/ CL=2 K4H280438B-TCA0 K4H280438B-TLA0 K4H280838B-TCA0 K4H280838B-TLA0 K4H281638B-TCA0 K4H281638B-TLA0 Temperature & Power Interface (VDD & VDDQ) REV. 1.31 Nov. 3. 2001 Speed Package Version ...

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... DDR SDRAM 1. Key Features 1.1 Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs - ...

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... DDR SDRAM 2. Package Pinout & Dimension 2.1 Package Pinout LDQS A13 LDM WE CAS RAS AP/A AP internally loaded to match DQ and DQS identically. 8Mb x 16 16Mb x 8 32Mb PIN TSOP(II (400mil x 875mil (0.65 mm PIN PITCH Bank Address BA0-BA1 Row Address A13 A13 ...

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... DDR SDRAM 2.2 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input *1 Input LDM,(U)DM BA0, BA1 Input Input I I/O LDQS,(U)DQS Supply Supply SS V Supply DD V Supply SS V Input REF *1 : DQ, DQS, DM signals may be floated to V DESCRIPTION Clock : CK and CK are differential clock inputs ...

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... DDR SDRAM E. 66pin TSOP-II Package Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’ Y OUT QUALITY #34 #33 22.22 ± 0.10 (10 × ) 0.65TYP 0.30± 0.08 0.65 ± 0.08 (10 × Units : Millimeters (10×) (10 × 0.125 - 0.10 MAX 0.25TYP [ 0.075 MAX ] 0× ~8× ...

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... DDR SDRAM 3. Functional Description 3.1 Simplified State Diagram MODE REGISTER SET POWER POWER APPLIED MRS IDLE CKEH POWER ACT DOWN CKEH CKE L ROW ACTIVE WRITE WRITEA READA READ WRITEA WRITE WRITEA READA PRE WRITEA PRE PRE PRE PRE ON CHARGE Figure 3. State diagram ...

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... DDR SDRAM 3.2 Basic Functionality 3.2.1 Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.) - Apply V before or at the same time Apply V Q before or at the same time as V ...

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... EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank pre- charge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register ...

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... DDR SDRAM Burst Length Address(A2, A1, A0 Table 4. Burst address ordering for burst length DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically) ...

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... DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register ...

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... The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. For both Deselect and NOP the device should finish the current operation when this com- mand is issued ...

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... The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is exe- cuted ...

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... The essential functionality that is required for the DDR SDRAM device is described in this chapter 3.3.1 Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation ...

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... DDR SDRAM 3.3.2 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued ...

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... DDR SDRAM 3.3.3 Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied ...

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... DQ s Figure 13. Read interrupted by a precharge timing When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. ...

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... DDR SDRAM 3.3.6 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric- tion that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied ...

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... For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read operation input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM. 5. Refer to "3.3.2 Burst write operation" 0 ...

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... Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank ...

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... DQS CAS Latency=2 The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required: 1. The BST command may only be issued on the rising edge of the input clock, CK. 2. BST is only a valid command during Read bursts. 3. BST during a Write burst is undefined and shall not be used. ...

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... The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). 3.3.10 DM masking The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data ...

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... DDR SDRAM 3.3.11 Read With Auto Precharge If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied ...

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... DDR SDRAM 3.3.12 Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal pre- charge begins after keeping tWR(min). ...

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... DDR SDRAM 3.3.13 Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris- ing edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh com- mand is applied ...

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... DDR SDRAM 3.3.14 Power down The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tck+tIS prior to row active command ...

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... Burst stop command is valid at every burst length sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 CKEn ...

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... DDR SDRAM 5. Functional Truth Table Current State CS RAS CAS PRECHARGE L H STANDBY ACTIVE L H STANDBY READ Address BA Op-Code, Mode-Add BA, CA BA Op-Code, Mode-Add BA, CA BA Op-Code, Mode-Add Table 9-1. Functional truth table - 36 - Command Action Burst Stop ...

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... DDR SDRAM Current State CS RAS CAS WRITE READ with L H AUTO PRECHARGE L H (READA WRITE with L H AUTO RECHARGE L H (WRITEA Address BA, CA BA Op-Code, Mode-Add BA, CA BA Op-Code, Mode-Add BA, CA BA Op-Code, Mode-Add Table 9-2. Functional truth table ...

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... DDR SDRAM Current State CS RAS CAS PRECHARG ING L H (DURING tRP ROW L H ACTIVATING L H (FROM ROW L L ACTIVE tRCD WRITE L H RECOVERING L H (DURING tWR tCDLR Address BA Op-Code, Mode-Add BA Op-Code, Mode-Add BA, CA BA Op-Code, Mode-Add Table 9-3 ...

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... DDR SDRAM Current State CS RAS CAS RE FRESHING MODE L H REGISTER L H SETTING Address BA Op-Code, Mode-Add BA Op-Code, Mode-Add Table 9-4. Functional truth table - 39 - Command Action Burst Stop ILLEGAL READ/WRITE ILLEGAL Active ILLEGAL PRE/PREA ILLEGAL Refresh ILLEGAL MRS ...

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... DDR SDRAM CKE CKE Current State n-1 n SELF REFRESHING POWER ALL BANKS IDLE ANY STATE H H other than listed above ABBREVIATIONS : H=High Level, L=Low level, X=Don t Care Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. ...

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... DDR SDRAM 6. Absolute Maximum Rating Parameter Voltage on any pin relative to V Voltage on V & V supply relative DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. ...

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... DDR SDRAM Notes 1. Includes 25mV margin for DC offset on V bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes both of which may result in V REF 2.V is not applied directly to the device and must track variations in the DC level of V REF the magnitude of the difference between the input level on CK and the input level on CK. ...

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... DDR SDRAM 7.3 DDR SDRAM I spec table DD 32Mx4 K4H280438B-TCA2 (DDR266A) Symbol typical IDD0 100 IDD1 125 IDD2P 25 IDD2F 45 IDD2Q 35 IDD3P 25 IDD3N 50 IDD4R 165 IDD4W 170 IDD5 185 IDD6 Normal 2 Low power 1 IDD7A 300 16Mx8 K4H280838BT-CA2 (DDR266A) Symbol typical IDD0 100 ...

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... K4H281638B-TCA0 (DDR200) Unit typical worst 90 100 mA 115 135 150 185 mA 160 200 mA 180 200 280 330 mA REV. 1.31 Nov. 3. 2001 ...

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... DDR SDRAM DD7A I : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ Worst Case : Vdd = 2.7V, T= 10’ Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4 ...

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... DDR SDRAM 8.2 AC Overshoot/Undershoot specification 8.2.1 Overshoot/Undershoot specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot (See Figure 1): Maximum peak amplitude allowed for undershoot (See Figure 1): The area between the overshoot signal and VDD must be less than or ...

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... DDR SDRAM 8.2.2 Overshoot/Undershoot specification for Data Pins Parameter Maximum peak amplitude allowed for overshoot (See Figure 2): Maximum peak amplitude allowed for undershoot (See Figure 2): The area between the overshoot signal and VDD must be less than or equal to (See Figure 2): ...

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... DDR SDRAM 8.3 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay ...

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... DDR SDRAM Parameter Output Slew Rate Matching Ratio (rise to fall) Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active command ...

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... DDR SDRAM 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 This derating table is used to increase t based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) ...

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... DDR SDRAM 9. AC Operating Test Conditions (V =2.5V, V =2.5V DDQ A Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition 10. Input/Output Capacitance (V =2.5, V =2.5V DDQ ...

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... DDR SDRAM 11. IBIS: I/V Characteristics for Input and Output Buffers 11.1 Normal strength driver 1. The full variation in driver pulldown current from minimum to maximum process, temperature, and voltage will lie within the outer bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a ...

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... DDR SDRAM Pulldown Current (mA) Voltage Typical Typical (V) Low 0.1 6.0 0.2 12.2 0.3 18.1 0.4 24.1 0.5 29.8 0.6 34.6 0.7 39.4 0.8 43.7 0.9 47.5 1.0 51.3 1.1 54.1 1.2 56.2 1.3 57.9 1.4 59.3 1.5 60.1 1.6 60.5 1 ...

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... Thenominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. ...

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... DDR SDRAM Pulldown Current (mA) Voltage Typical Typical (V) Low 0.1 3.4 0.2 6.9 0.3 10.3 0.4 13.6 0.5 16.9 0.6 19.6 0.7 22.3 0.8 24.7 0.9 26.9 1.0 29.0 1.1 30.6 1.2 31.8 1.3 32.8 1.4 33.5 1.5 34.0 1.6 34.3 1 ...