K4H511638C-ZLB3 Samsung Semiconductor, K4H511638C-ZLB3 Datasheet
K4H511638C-ZLB3
Specifications of K4H511638C-ZLB3
Related parts for K4H511638C-ZLB3
K4H511638C-ZLB3 Summary of contents
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 512Mb C-die DDR SDRAM Specification 60 FBGA with Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... DC Operating Conditions ........................................................................................................10 12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11 13.0 Input/Output Capacitance ......................................................................................................11 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12 15.0 DDR SDRAM IDD spec table ..................................................................................................13 16.0 AC Operating Conditions .......................................................................................................14 17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15 19.0 AC Timming Parameters & ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) Revision History Revision Month Year 0.0 October 2004 - First version for internal review 1.0 February 2005 - Release the Rev. 1.0 spec 1.1 June 2005 - Changed master format. DDR SDRAM History Rev. 1.1 June. 2005 ...
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... Maximum burst refresh cycle : 8 • 60Ball FBGA Pb-Free package • RoHS compliant 2.0 Ordering Information Part No. K4H510438C-ZC/LCC K4H510438C-ZC/LB3 K4H510838C-ZC/LCC K4H510838C-ZC/LB3 K4H511638C-ZC/LCC K4H511638C-ZC/LB3 3.0 Operating Frequencies Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP Org. Max Freq. CC(DDR400@CL=3) 128M x 4 B3(DDR333@CL=2.5) CC(DDR400@CL=3) 64M x 8 B3(DDR333@CL=2 ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 4.0 Ball Description (Bottom 128M VSSQ VDDQ VSSQ 3 VSS DQ3 VDD DQ0 8 NC VSSQ VDDQ 9 VDDQ NC 64M VSSQ NC 2 DQ7 VDDQ VSSQ 3 VSS DQ6 DQ5 VDD DQ1 DQ2 8 DQ0 VSSQ VDDQ 9 VDDQ NC 32M VSSQ DQ14 ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 5.0 Package Physical Dimension #A1 WINDOW MOLD AREA 0.80 x2 (Datum 60-∅0.45 ± 0.05 0. 4-CORNER MARK(option) 10.00 ± 0.10 Top view 10.00 ± 0. 0.80 6.40 0. 3.20 #A1 MARK(option) 1. 0.80 (0.90) (0.90) (1.80) (Datum A) Bottom view 60Ball FBGA 512Mb Package Dimension DDR SDRAM 1 ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 6.0 Block Diagram ( 32Mb x 4 Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE / 16Mb 8Mb x 16 x4/8/16 CK, CK Data Input Register Serial to parallel x8/16/32 16Mx8/ 8Mx16/ 4Mx32 16Mx8/ 8Mx16/ 4Mx32 16Mx8/ 8Mx16/ 4Mx32 16Mx8/ 8Mx16/ 4Mx32 Column Decoder Latency & ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 7.0 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(UDM) Input BA0, BA1 Input 12] Input DQ I/O LDQS,(U)DQS I VDDQ Supply VSSQ Supply VDD Supply VSS Supply VREF Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK ...
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... DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 CKEn CS ...
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... Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks Double Data Rate SDRAM 9.0 General Description The K4H510438C / K4H510838C / K4H511638C is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Syn- chronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 12.0 DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A IDD1 : Operating current: One bank operation 1. Typical Case: Fro DDR200,266,333: Vdd = 2.5V, T=25’C; For DDR400: Vdd=2.6V,T=25’C Worst Case : Vdd = 2.7V, T= 10’c 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle ...
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... Normal IDD6 Low power IDD7A 128Mx4 (K4H510438C) 120 150 155 175 220 5 3 385 64Mx8 (K4H510838C) 120 150 155 175 220 5 3 385 32Mx16 (K4H511638C) 120 160 190 215 220 5 3 400 DDR SDRAM (V =2.7V 10°C) DD Unit Notes B3(DDR333@CL=2.5) 105 mA 135 ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 16.0 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 19.0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2 ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 20.0 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM ...
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... DQS will be tran sitioning from High logic LOW previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate ≥ 1.0 V/ns 16. For command/address input slew rate ≥ ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) Component Notes 17. For CK & CK slew rate ≥ 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) 22.0 System Notes a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Output Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. Output Figure 3 : Pulldown slew rate test load c ...
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... DDR SDRAM Output Driver V-I Characteristics DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input into simulation tools ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 51 ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16 0.0 Pullup Characteristics for Weak Output Driver 0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Pulldown Characteristics for Weak Output Driver Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) 1.0 2.0 1.0 2.0 DDR SDRAM ...
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... DDR SDRAM 512Mb C-die (x4, x8, x16) Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 29 ...