IS43R32400A-6B ISSI, Integrated Silicon Solution Inc, IS43R32400A-6B Datasheet - Page 4

• Manufacturer Part Number: IS43R32400A-6B
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32400A-6B

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 850ps
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 420mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IS43R32400A
PIN FUNCTIONS
4
Symbol
A0-A11
BA0, BA1
CAS
CKE
CLK, CLK
CS
DM0-DM3
DQS0-DQS3
DQ0-DQ31
NC
RAS
WE
VDDQ
VDD
VREF
VSSQ
VSS
Type
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input/Output Pin
Input/Output Pin
—
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address inputs are sampled during several commands. During an Active
command, A0-A11 select a row to open. During a Read or Write command,
A0-A7 select a starting column for a burst. During a Pre-charge command,
A8 determines whether all banks are to be pre-charged, or a single bank.
During a Load Mode Register command, the address inputs select an
operating mode.
Bank Address inputs are used to select a bank during Active, Pre-charge,
Read, or Write commands. During a Load Mode Register command, BA0
and BA1 are used to select between the Base or Extended Mode Register
CAS is Column Access Strobe, which is an input to the device command
along with RAS and WE. See “Command Truth Table” for details.
Clock Enable: CKE High activates and CKE Low de-activates internal clock
signals and input/output buffers. When CKE goes Low, it can allow Self
Refresh, Pre-charge Power Down, and Active Power Down. CKE must be
High during entire Read and Write accesses. Input buffers except CLK,
CLK, and CKE are disabled during Power Down. CKE uses an SSTL 2
input, but will detect a LVCMOS Low level after VDD is applied.
All address and command inputs are sampled on the rising edge of the
clock input CLK and the falling edge of the differential clock input CLK.
Output data is referenced from the crossings of CLK and CLK.
The Chip Select input enables the Command Decoding block of the device.
When CS is disabled, a NOP occurs. See “Command Truth Table” for
details. Multiple DDR SDRAM devices can be managed with CS.
These are the Data Mask inputs. During a Write operation, the Data Mask
input allows masking of the data bus. DM is sampled on each edge of DQS.
There are four Data Mask input pins for the x32 DDR SDRAM. Each input
applies to DQ0-DQ7, DQ8-DQ15, DQ16-DQ23, or DQ24-DQ31.
These are the Data Strobe inputs. The Data Strobe is used for data capture.
During a Read operation, the DQS output signal from the device is edge-
aligned with valid data on the data bus. During a Write operation, the DQS
input should be issued to the DDR SDRAM device when the input values on
DQ inputs are stable. There are four Data Strobe pins for the x32 DDR
SDRAM. Each of the four Data Strobe pins applies to DQ0-DQ7, DQ8-
DQ15, DQ16-DQ23, or DQ24-DQ31.
The pins DQ0 to DQ31 represent the data bus. For Write operations, the
data bus is sampled on Data Strobe. For Read operations, the data bus is
sampled on the crossings of CK and CK.
No Connect: This pin should be left floating. These pins could be used for
256Mbit or higher density DDR SDRAM.
RAS is Row Access Strobe, which is an input to the device command
along with CAS and WE. See “Command Truth Table” for details.
WE is Write Enable, which is an input to the device command along with
RAS and CAS. See “Command Truth Table” for details.
VDD is the device power supply.
VREF is the reference voltage for SSTL 2.
VSS is the device ground.
VDDQ is the output buffer power supply.
VSSQ is the output buffer ground.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ISSI
Rev. 00D
02/15/06
®