IS43R32400A-6B ISSI, Integrated Silicon Solution Inc, IS43R32400A-6B Datasheet
IS43R32400A-6B
Specifications of IS43R32400A-6B
Related parts for IS43R32400A-6B
IS43R32400A-6B Summary of contents
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... CLK. Commands are registered on the positive edges of CLK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2. IS43R32400A 1M x32x4 Banks ...
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... IS43R32400A FUNCTIONAL BLOCK DIAGRAM ( CLK COMMAND CLK DECODER CKE & CS CLOCK RAS GENERATOR CAS WE MODE REGISTER A11 14 A10 ROW BA0 ADDRESS BA1 LATCH 14 COLUMN ADDRESS LATCH 8 BURST COUNTER COLUMN ADDRESS BUFFER 2 32) X REFRESH CONTROLLER SELF REFRESH CONTROLLER REFRESH COUNTER ROW ADDRESS ...
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... IS43R32400A PIN CONFIGURATION PACKAGE CODE: B 144-BALL FBGA (Top View) (12. 12.00 mm Body, 0.8 mm Ball Pitch DQS0 DM0 B DQ4 VDDQ C DQ6 DQ5 D DQ7 VDDQ E DQ17 DQ16 F DQ19 DQ18 G DQS2 DM2 H DQ21 DQ20 J DQ22 DQ23 K CAS WE L RAS Note: Vss balls inside the dotted box are optional for purposes of thermal dissipation. ...
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... IS43R32400A PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK, CLK Input Pin CS Input Pin DM0-DM3 Input Pin DQS0-DQS3 Input/Output Pin DQ0-DQ31 Input/Output Pin NC — RAS Input Pin WE Input Pin VDDQ Power Supply Pin ...
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... IS43R32400A COMMAND TRUTH TABLE Function CKE ( CKE (n) Device Deselect (NOP) No Operation (NOP) (2) Burst Stop (3) Read (3) Write Bank and Row Activate Pre-charge select bank Pre-charge all banks Load Mode Register (Base) Load Extended Mode Register Auto Refresh Self Refresh Notes VIH VIL VIH or VIL Valid Data. ...
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... IS43R32400A DETAILED COMMAND TRUTH TABLE - SAME BANKS Function (n) Command (n) NOP or Continue Deselect previous operation NOP or Continue NOP previous operation Activate row Active Issue Auto Refresh Auto Refresh Load the Base/ Load Mode Register Extended Mode Register Start Read Burst Read Read ...
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... IS43R32400A DETAILED COMMAND TRUTH TABLE - DIFFERENT BANKS (bank b, then bank g) Function (n) Command (n) NOP or Continue Deselect previous operation NOP or Continue NOP previous operation Issue any command to Any command bank g otherwise valid Start Read Burst in Read bank g Read Read Read Read Start Write Burst in bank g ...
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... IS43R32400A DETAILED COMMAND TRUTH TABLE - DIFFERENT BANKS (bank b, then bank g) Function (n) Command (n) Start Pre-charge Pre-charge Pre-charge Pre-charge Pre-charge Pre-charge Note Write command may be terminated only at the completion of the Read burst. However, a Burst Terminate can be transmitted to end the Read burst early so that a Write command can be asserted. ...
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... IS43R32400A ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX Input Voltage, Reference Voltage IN REF V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG Notes: 1 ...
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... IS43R32400A DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Operating Current Operating Current Precharge Power-Down Standby Current I Idle Standby Current Active Power-Down Standby Current I Active Standby Current Operating Current Burst Read I Operating Current Burst Write I Auto Refresh Current Self Refresh Current Operating Current 7 DD Notes: 1.Operating outside the “ ...
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... IS43R32400A AC ELECTRICAL CHARACTERISTICS (V Symbol Parameter t Clock Cycle Time CK t Clock High Level Width CH t Clock Low Level Width CL DQS-Out Access Time from CLK, CLK t DQSCK Output Access Time from CLK, CLK DQS-DQ Skew DQSQ t Read Preamble RPRE t Read Postamble RPST t CLK to Valid DQS-In ...
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... IS43R32400A AC TEST CONDITIONS Output Load Z = 25Ω Output TEST CONDITIONS Parameter Input Signal Levels Input Signal Slew Rate Input Timing Reference Level Output Timing Measurement Reference Level CLK and CLK Signal Maximum Peak Swing Reference Level of Input/Ouput Signals 0 DDQ 25Ω 0 REF ...
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... IS43R32400A FUNCTIONAL DESCRIPTION The 128Mbit DDR SDRAM is a high-speed CMOS device with four banks that operate at 2.5V. Each 32Mbit bank is organized as 4,096 rows of 256 columns for the x32 options. Pre-fetch architecture allows Read and Write accesses to be double-data rate and burst oriented. Accesses start at a selected column location and continue every half-clock cycle for a programmed number of times ...
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... IS43R32400A MODE REGISTER DEFINITION The mode register allows configuration of the operat- ing mode of the DDR SDRAM. This register is loaded as a step in the normal initialization of the device. The Load Mode Register command samples the values on inputs A0-A11, BA0 (Low) and BA1 (Low) and stores them as register values M0-M13 ...
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... IS43R32400A BURST LENGTH The highest access throughput of this device can be achieved by using a burst of either Read or Write accesses. The number of accesses in each burst would be pre-configured full page as shown in Mode Register Definition (bits M0-M2). When a Read or Write command is given to the device, the address bits A0-A7 (x32) select the block of columns and the starting column for the subsequent burst ...
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... IS43R32400A EXTENDED MODE REGISTER DEFINITION The Extended Mode Register is a second register to enable additional functions of the DDR SDRAM. This register is loaded as a step in the normal initialization of the device. The Load Extended Mode Register command samples the values on inputs A0-A11, BA0 (High) and BA1 (Low) and stores them as register values E0-E13 ...
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... IS43R32400A COMMANDS All commands described in this section should be issued only when the initialization sequence is obeyed. Deselect This feature blocks unwanted commands from being executed. Chip select (CS) must be taken High to cause Deselect. Operations that are underway are not affected. No Operation (NOP) NOP is a command that prevents new commands from being executed ...
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... IS43R32400A Auto Refresh The DDR SDRAM is issued the Auto Refresh com- mand during normal operation to maintain data in the memory array. All the banks must be idle for the command to be executed. The device has 4096 refresh cycles every 32ms. Self Refresh To issue the Self Refresh command, CKE must be Low ...
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... IS43R32400A Write Operation A Write command starts a burst from an activated row. The Write command is depicted in the figure. As CLK goes High, CS, WE, and CAS are Low, while CKE and RAS are High. The values on the inputs BA0 and BA1 specify the bank to access, and the address inputs specify the starting column in the open row ...
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... IS43R32400A Timing Waveforms Figure 1. AC Parameters for Read Timing ( Burst Length =4) Figure 2. AC Parameters for Write Timing (Burst Length=4 ) CK# CK CMD A0-11, DQS Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00D 02/15/06 ...
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... IS43R32400A Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00D 02/15/06 ISSI ® 21 ...
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... IS43R32400A Figure 6. Write with Auto Precharge (Burst Length = 4) Figure 7. Read Burst Interrupt by Read (CAS Letancy =5, Burst Length = 4 ) Figure 8. Write Interrupted by Write (Burst Length =4) Figure 9. Auto Refresh Timing 22 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00D 02/15/06 ...
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... IS43R32400A Figure 11. Precharge Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00D 02/15/06 t MRD ISSI ® 23 ...
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... MHz 6 24 Order Part No. Package IS43R32400A-5B 144-ball FBGA IS43R32400A-5BL 144-ball FBGA, Lead-free IS43R32400A-6B 144-ball FBGA IS43R32400A-6BL 144-ball FBGA, Lead-free Order Part No. Package IS43R32400A-6BI 144-ball FBGA IS43R32400A-6BLI 144-ball FBGA, Lead-free Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00D 02/15/06 ...
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PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (144-Ball SEATING PLANE mBGA - 12mm ...