IS42S16400-8TL ISSI, Integrated Silicon Solution Inc, IS42S16400-8TL Datasheet

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IS42S16400-8TL

Manufacturer Part Number
IS42S16400-8TL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S16400-8TL

Organization
4Mx16
Density
64Mb
Address Bus
14b
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
IS42S16400
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 166, 143, 125, 100 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package 400-mil 54-pin TSOP II
PIN DESCRIPTIONS
This document contains TARGET SPECIFICATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
TARGET SPECIFICATION Rev. 00A
06/07/00
A0-A11
BA0, BA1
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
positive clock edge
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Address Input
Bank Select Address
DESCRIPTION
ISSI
as a 1,048,576 bits x 16-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
's 16Mb Synchronous DRAM IS42S16400 is organized
GNDQ
GNDQ
VCCQ
VCCQ
LDQM
VCC
VCC
VCC
CAS
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
BA0
BA1
A10
WE
CS
A0
A1
A2
A3
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
TARGET SPECIFICATION
ISSI
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
JUNE 2000
GND
I/O15
GNDQ
I/O14
I/O13
VCCQ
I/O12
I/O11
GNDQ
I/O10
I/O9
VCCQ
I/O8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
®
1

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IS42S16400-8TL Summary of contents

Page 1

... ISSI TARGET SPECIFICATION DESCRIPTION ISSI 's 16Mb Synchronous DRAM IS42S16400 is organized as a 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. ...

Page 2

... IS42S16400 PIN FUNCTIONS Pin No. Symbol Type A0-A11 Input Pin 22, 35 20, 21 BA0, BA1 Input Pin CAS 17 Input Pin 37 CKE Input Pin 38 CLK Input Pin CS 19 Input Pin 10, I/O0 to I/O Pin 11,13, 42, 44, 45, I/O15 47, 48, 50, 51, 53 15, 39 LDQM, Input Pin UDQM RAS ...

Page 3

... IS42S16400 FUNCTIONAL BLOCK DIAGRAM CLK CKE COMMAND CS RAS DECODER & CAS WE CLOCK MODE GENERATOR A11 REGISTER 11 A10 ROW BA0 ADDRESS BA1 LATCH 11 COLUMN ADDRESS LATCH 8 BURST COUNTER COLUMN ADDRESS BUFFER Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev. 00A 06/07/00 ...

Page 4

... IS42S16400 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage CC MAX V Maximum Supply Voltage for Output Buffer CCQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...

Page 5

... IS42S16400 DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL (1,2) I Operating Current Precharge Standby Current CC I 2PS (In Power-Down Mode Precharge Standby Current CC I 2NS (In Non Power-Down Mode Active Standby Current ...

Page 6

... IS42S16400 AC CHARACTERISTICS (1,2,3) Symbol Parameter t 3 Clock Cycle Time Access Time From CLK ( CLK HIGH Level Width CHI t CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time ( Input Data Setup Time DS t Input Data Hold Time ...

Page 7

... IS42S16400 AC CHARACTERISTICS (1,2,3) Symbol Parameter t 3 Clock Cycle Time Access Time From CLK ( CLK HIGH Level Width CHI t CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time ( Input Data Setup Time DS t Input Data Hold Time ...

Page 8

... IS42S16400 OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit setup mode PED t DQM to input data delay DQD t DQM to data mask during WRITEs ...

Page 9

... IS42S16400 OPERATIONAL DESCRIPTION tbd GENERAL TRUTH TABLE tbd TIMING DIAGRAMS tbd Integrated Silicon Solution, Inc. — 1-800-379-4774 TARGET SPECIFICATION Rev. 00A 06/07/00 ISSI ® 9 ...

Page 10

... Speed (ns) Order Part No. 6 IS42S16400-6T 7 IS42S16400-7T 8 IS42S16400-8T 10 IS42S16400-10T Speed (ns) Order Part No. 6 IS42S16400-6TI 7 IS42S16400-7TI 8 IS42S16400-8TI 10 IS42S16400-10TI Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI Package 400-mil TSOP II 400-mil TSOP II 400-mil TSOP II 400-mil TSOP II Package 400-mil TSOP II 400-mil TSOP II ...

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