AD7769JP-REEL Analog Devices Inc, AD7769JP-REEL Datasheet - Page 4

• Manufacturer Part Number: AD7769JP-REEL
• Manufacturer: Analog Devices Inc

Specifications of AD7769JP-REEL

• Lead Free Status / Rohs Status: Supplier Unconfirmed

AD7769
TIMING CHARACTERISTICS
Parameter
ADC /DAC CONTROL TIMING
ADC CONVERSION TIMING
ADC READ TIMING
DAC WRITE TIMING
NOTES
1
2
3
4
Specifications subject to change without notice.
See Figures 11, 12 and 13.
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
t
t
10
14
Figure 3. Load Circuit for RD and WR to INT Delay Test
CS to WR Setup Time
CS to WR Hold Time
ADC/DAC to WR Setup Time
ADC/DAC to WR Hold Time
CHA/CHB to WR Setup Time
CHA/CHB to WR Hold Time
WR Pulse Width
Using External Clock
Using Internal Clock
CS to RD Setup Time
CS to RD Hold Mode
RD to Data Valid Delay
Bus Relinquish Time after RD High
RD to INT High Delay
RD Pulse Width
Data Valid to WR Setup Time
Data Valid to WR Hold Time
WR to DAC Output Settling Time
and t
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
WR to INT Low Delay
WR to INT Low Delay
WR to INT High Delay
WR to Data Valid Delay
Figure 1. Load Circuits for Data Access Time Test
13
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
3
4
1, 2
Label
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
8
9
9
10
10
11
12
13
13
14
15
15
16
17
18
19
(V
For ADC and DAC, V
CC
= +5 V
Limit at Limit at
+25 C
0
0
0
0
0
0
80
2.6
1.9/3.0
85
120
t
t
0
0
15/65
30/100
15/65
80
110
t
65
15
4
8
8
13
+70
+110
5%; V
T
0
0
0
0
0
0
80
2.6
1.9/3.0
85
120
t
t
0
0
15/65
30/100
15/65
80
110
t
65
20
4
BIAS
8
8
13
MIN
+70
+110
–4–
DD
= +5 V, V
= +12 V
, T
MAX
Figure 2. Load Circuits for Bus Relinquish Time Test
Figure 4. Load Circuit for DAC Settling Time Test
SWING
Units
ns min
ns min
ns
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns min/max
ns min/max
ns min/max
ns max
ns max
ns min
ns nıin
ns min
10%; AGND [ADC] = AGND [DAC] = DGND = 0 V.
s max
s min/max
s max
= +2.5 V.)
Load Circuit of Figure 3, C
Load Circuit of Figure 3, C
Typically 2.5 s
Load Circuit of Figure 3, C
Load Circuit of Figure 3, C
Load Circuit of Figure 1, C
Load Circuit of Figure 1, C
Load Circuit of Figure 1, C
Load Circuit of Figure 1, C
Load Circuit of Figure 2
Load Circuit of Figure 3, C
Load Circuit of Figure 3, C
Determined by t
Load Circuit of Figure 4
Test Conditions/Comments
13
L
L
L
L
L
L
L
L
L
L
= 20 pF
= 20 pF
= 20 pF
= 20 pF
= 100 pF
= 20 pF
= 100 pF
= 100 pF
= 20 pF
= 100 pF
REV. A