FWIXC1100BD Intel, FWIXC1100BD Datasheet - Page 4

• Manufacturer Part Number: FWIXC1100BD
• Manufacturer: Intel

Specifications of FWIXC1100BD

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

4.0
5.0
6.0
7.0
A
Intel
Hardware Design Guidelines
4
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
3.12
3.13
PBGA Package..........................................................................................................55
4.1
4.2
General PCB Guide ...................................................................................................57
5.1
5.2
5.3
5.4
5.5
General Layout and Routing Guide ...........................................................................61
6.1
6.2
6.3
6.4
Critical Routing Topologies ......................................................................................73
7.1
7.2
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
Design Checklist......................................................................................................81
3.11.1 Interface Signals ....................................................................................48
3.11.2 Pull-Up/Down Resistors ...........................................................................48
Clock ...............................................................................................................48
3.12.1 Clock Signals .........................................................................................49
3.12.2 Using Oscillator ......................................................................................49
3.12.3 Design Notes..........................................................................................49
3.12.4 Block Diagram........................................................................................50
Power ..............................................................................................................50
3.13.1 Power Supply Requirements .....................................................................51
3.13.2 +3.3 V DC .............................................................................................51
3.13.3 +1.3 V DC .............................................................................................51
3.13.4 Power Up...............................................................................................51
PBGA Package Overview .....................................................................................55
Signal Grouping.................................................................................................55
PCB Overview ...................................................................................................57
General Recommendations..................................................................................57
Component Selection .........................................................................................57
Component Placement........................................................................................57
Stack Up Selection .............................................................................................58
Overview ..........................................................................................................61
General Layout Guidelines...................................................................................61
6.2.1
General Routing Guides ......................................................................................63
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Devices’ Decoupling ...........................................................................................70
6.4.1
PC133 SDRAM Topologies ...................................................................................73
7.1.1
PCI Topologies ..................................................................................................75
7.2.1
7.2.2
7.2.3
Checklist ..........................................................................................................81
SDRAM Interface ...............................................................................................81
PCI Interface.....................................................................................................82
High-Speed Serial Interface ................................................................................83
MII Interface.....................................................................................................84
UTOPIA-2 Interface............................................................................................85
Expansion Bus Interface .....................................................................................86
A.7.1
UART Interface ..................................................................................................88
General Component Spacing ....................................................................62
Clock Signal Considerations......................................................................65
LAN Signal Considerations........................................................................66
USB Considerations.................................................................................67
Crosstalk ...............................................................................................67
EMI Design Considerations .......................................................................68
Trace Impedance ....................................................................................69
Power and Decoupling .............................................................................69
General Decoupling/Bypass Guidelines.......................................................70
PC 133 SDRAM Clock...............................................................................74
Trace Length Limits.................................................................................78
Routing Guidelines ..................................................................................78
Signal Loading........................................................................................79
Expansion Bus Configuration Strappings ....................................................87
Intel
®
IXP42X product line and IXC1100 control plane processors—Contents
Document Number: 252817-008US
December 2007