MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 49

no-image

MCC501RX200TD0B

Manufacturer Part Number
MCC501RX200TD0B
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MCC501RX200TD0B

Package Type
BGA
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCC501RX200TD0B
Manufacturer:
FREESCALE
Quantity:
20 000
Table 23 BMU SDRAM Interface Signals (continued)
Table 24 TLU SRAM Interface Signals
SIGNAL NAME
MDCLK
TOTAL PINS
SIGNAL NAME
TD0 - TD63
TA0 - TA21
TA18x - TA21x
TCE0X - TCE3X
TWE0X - TWE3X
TCLKI
TOTAL PINS
TLU SRAM Interface
PIN #
N1, L1, J1, H1, M2, K2, I2, G2, N2, L2, J2, H2, L3, J3,
H3, G4, 04, M4, K4, I4, L4, J4, H4, G6, N5, L5, J5, H5,
N6, L6, I6, H6, K6, J6, M6, H7, L7, J7, H8, N8, M8, K8,
I8, G8, N7, L8, J8, H9, L9, J9, J10, G10, P9, O8, L10,
H10, O10, N9, L11, I10, M10, K10, J11, H11
R1, P1, S2, Q2, O2, R2, P2, R3, P3, N3, S4, Q4, R4, P4,
N4, R5, P5, S6, R6, Q6, P6, O6
T8, Q8, R7, P7
P8, R8, S8, T9
Q10, R9, S10, T10
M12
PIN #
J17
Signals
The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz
using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to
64Mbits. The TLU SRAM interface signals are described in
Table 25 Memory Bank Selection
SIZE
4Mbit
8Mbit
16Mbit
BANK 1
CE2
TA18x
TA19x
TA20x
TOTAL
1
161
CHIP SELECT (SIGNALS TA18X THROUGH TA21X)
CE2X
TA19
TA20
TA21
TYPE
LVTTL
BANK 2
CE2
TA18
TA19
TA20
TOTAL
64
22
4
4
4
1
99
I/O
I
CE2X
TA19
TA20
TA21
TYPE
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
SIGNAL DESCRIPTION
Clock: MDCLK is driven by the system clock. All
SDRAM input signals are sampled on the positive
edge of the MDCLK. MDCLK also increments the
internal burst counter and controls the output
registers.
Pin Descriptions Grouped by Function
I/O
I/O
O
O
O
O
I
BANK 3
CE2
TA18x
TA19x
TA20x
SIGNAL DESCRIPTION
TLU Memory Data
TLU Memory Address
Data Parity
TLU Memory Chip Enable
TLU Memory Write Enable
TLU Clock Input
Table 24
CE2X
TA19x
TA20x
TA21x
.
BANK 4
CE2
TA18
TA19
TA20
CE2X
TA19x
TA20x
TA21x
V 04
49

Related parts for MCC501RX200TD0B