NHIXP433AD Intel, NHIXP433AD Datasheet - Page 14

• Manufacturer Part Number: NHIXP433AD
• Manufacturer: Intel

Specifications of NHIXP433AD

• Core Operating Frequency: 533MHz
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

12.
Problem:
Implication:
Workaround:
Status:
13.
Problem:
Implication:
Workaround:
Status:
14.
Problem:
Implication:
Workaround:
Status:
15.
Problem:
Implication:
Workaround:
Intel
Specification Update
14
®
IXP43X Product Line of Network Processors
Ethernet Coprocessors — Address Filtering Logic Ignores the Second
to Last Nibble of the Destination Address
The Intel
configured by the Intel
second last nibble of the destination address regardless of the packet type (unicast,
multicast, broadcast), that is, Destination Address: 11 22 33 44 55 x6. The reason it is
the second last is that the address is transmitted on the line with high nibble first and
then the low nibble.
Some Ethernet frames with wrong destination address can get through the Address
Filter.
A software workaround is possible using the ixEthDb filtering capabilities.
No Fix.
Ethernet MACs Detect Late Collision Earlier Than Ethernet 802.3
Specifications
On an improperly designed network, when a collision occurs on the threshold of the
smallest valid Ethernet frame, it is detected as a late collision rather than an early
collision.
The collided frame will not be retried up to the programmed retry count and will be
dropped.
Cable lengths, number of repeaters, and other parameters that affect the network
design must be planned not to operate on the boundary of the Ethernet specifications.
No Fix.
Read of PCI Controllers BAR 32'h XXFF_FFFC Rd[N] Corrupts
Subsequent Rd[N+1]
If specifically reading the ‘last word’ address of a BAR register, read(n), and if that BAR
register is set up adjacent to undefined memory space (that is, not adjacent to another
BAR register), this read(n) will complete correctly, but will cause data corruption in the
subsequent read (n+1).
Upon the next subsequent external PCI master read Rd[N+1], the PCI controller
returns incorrect read data of Rd[N].
Avoid reading the last word of the BAR or avoid reading this one BAR entirely. The
setup could be changed such that the BAR registers are adjacent to each other in
memory space and place the config BAR 4 on top of the final BAR so that no “last word”
address in each memory address BAR0-3 is adjacent to undefined memory space. For
example:
No Fix.
UART Operating in Non-FIFO Mode Can Falsely Receive Overrun Error
If the UART is operating in non-FIFO mode, there is a possibility of falsely receiving an
Overrun Error under certain conditions even though an overrun did not occur.
An erroneous interrupt to the Intel XScale processor may occur indicating that data was
lost in the UART.
Using the UART in FIFO mode or in non-FIFO mode, the data should be rejected and
resent.
BAR4 - config BAR: highest address
BAR3
BAR2
BAR1
BAR0 - lowest address
®
IXP43X Product Line of Network Processors has an Ethernet coprocessor
®
IXP400 Software. The Ethernet coprocessor logic ignores the
4.0 Non-Intel XScale
Order Number: 316847; Revision:
®
Technology Errata Descriptions
December 2008
005US