NHIXP433AD Intel, NHIXP433AD Datasheet - Page 13

• Manufacturer Part Number: NHIXP433AD
• Manufacturer: Intel

Specifications of NHIXP433AD

• Core Operating Frequency: 533MHz
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

4.0 Non-Intel XScale
Workaround:
Status:
9.
Problem:
Implication:
Workaround:
Status:
10.
Problem:
Implication:
Workaround:
Status:
11.
Problem:
Implication:
Workaround:
Status:
December 2008
Order Number: 316847; Revision:
not equal to 64 bytes, and the entry in the length field is less than 46, but not zero.
None.
No Fix.
False PCI DMA Completion Notification Causing Data Corruption
The PADC1, PADC0, APDC1, and APDC0 complete bits in the PCI_DMACTRL register will
not be cleared under certain conditions when the Intel XScale
write-1-to-clear (W1C) to the appropriate bit. If another PCI DMA transfer is initiated
after the clear to the PCI_DMACTRL register, an indication of complete will occur before
the DMA transfer has been finished (because the complete bit may not have been
cleared).
DMA data will not be transferred as programmed in the PCI DMA registers.
Following two workarounds are available:
No Fix.
PCI Hangs With a Multiple Inbound Error Condition
The PCI controller may lock up if there are multiple errors occurring around two
different inbound PCI transactions.
A lock-up will occur when:
AND
The PCI controller will continue to retry all inbound transactions, and the PCI bus will
lock up.
When the PCI controller has an AHB error logged (PCI_ISR.AHBE = 1), a PCI parity
error is logged (PCI_SRCR.DPE = 1), and the PCI controller retries every inbound
transaction; the system board must reset the IXP43X network processors.
No Fix.
UART — Break Condition Asserted Too Early If Two Stop Bits are Used
The break condition is asserted after the time of the first stop bit, even if two stop bits
are used.
In the following scenario, a break condition will be raised on valid data:
Do not use two stop bits.
No Fix.
1. An inbound PCI read that targets an internal slave such as the expansion bus or
2. A second inbound PCI transfer is started while the first PCI read is still pending and
1. A byte consisting only zeros is received.
2. The first stop bit sampling is missed, and only the second one is sampled.
• Mask the PADC/APDC enables in the PCI_INTEN register and use software to poll
• If interrupts are preferred, after writing a 1 to clear the appropriate complete bit in
the EN (bit 31) of the appropriate PCI_ATPDMA0_LENGTH, PCI_PTADMA0_LENGTH
and PCI_ATPDMA1_LENGTH, PCI_PTADMA1_LENGTH register to indicate whether
the DMA transfer was completed.
the PCI_DMACTRL register, read the PCI_DMACTRL register back and ensure the
appropriate complete bit was cleared. If not cleared, repeat this step until the
appropriate complete bit is cleared.
Queue Manager results in an AHB error that occurs due to the PCI controller
generating an illegal AHB transfer type on the target.
the second PCI transfer detects a PCI address or data parity error.
®
Technology Errata Descriptions
005US
Intel
®
IXP43X Product Line of Network Processors
®
Processor performs a
Specification Update
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