NHIXP430AC Intel, NHIXP430AC Datasheet - Page 20

• Manufacturer Part Number: NHIXP430AC
• Manufacturer: Intel

Specifications of NHIXP430AC

• Core Operating Frequency: 400MHz
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

6.
Problem:
Workaround:
Status:
7.
Problem:
Workaround:
Status:
8.
Problem:
Intel
Specification Update
20
®
IXP43X Product Line of Network Processors
Disabling and Re-Enabling the MMU Can Hang the Processor or Cause
It to Execute the Wrong Code
When the MMU is disabled via the CP15 control register (CP15, CR1, opcode_2 = 0, bit
0) after being enabled, certain timing cases can cause the processor to hang. In
addition to this, re-enabling the MMU after disabling it can cause the processor to fetch
and execute code from the wrong physical address. To avoid these issues, the following
code sequence must be used whenever disabling the MMU or re-enabling it afterwards.
The following code sequence can be used to disable and/or re-enable the MMU safely.
The alignment of the mcr instruction that disables or re-enables the MMU must be
controlled carefully so that it resides in the first word of an instruction cache line.
No Fix.
Updating the JTAG Parallel Registers Requires an Extra TCK Rising
Edge
The IEEE 1149.1 specification states that the effect of updating all parallel JTAG
registers should be seen on the falling edge of TCK in the Update-DR state. The Intel
XScale processor parallel JTAG registers require an extra TCK rising edge to make the
update visible. Therefore, operations like hold-reset, JTAG break, and vector traps
require either an extra TCK cycle by going to Run-Test-Idle or by cycling through the
state machine again in order to trigger the expected hardware behavior.
When the JTAG interface is polled continuously, this erratum has no effect. If not, an
extra TCK cycle can be caused by going to Run-Test-Idle after writing a parallel JTAG
register.
No Fix.
Non-Branch Instruction in Vector Table May Execute Twice After a
Thumb Mode Exception
When an exception occurs in thumb mode and a non-branch instruction is executed at
the corresponding exception vector, that instruction may execute twice. The
instructions located at exception vectors must be branch instructions that go to the
appropriate handler, but the ARM architecture allows the FIQ handler to be placed
directly at the FIQ vector (0x0000001c/0xffff001c) without requiring a branch. Due to
@ The following code sequence takes r0 as a parameter. The value of r0 will be
@written to the CP15 control register to either enable or disable the MMU.
mcr p15, 0, r0, c10, c4, 1 @ unlock I-TLB
mcr p15, 0, r0, c8, c5, 0 @ invalidate I-TLB
mrc p15, 0, r0, c2, c0, 0 @ CPWAIT
mov r0, r0
sub pc, pc, #4
b 1f @ branch to aligned code
.align 5
1:
mcr p15, 0, r0, c1, c0, 0 @ enable/disable MMU, caches
mrc p15, 0, r0, c2, c0, 0 @ CPWAIT
mov r0, r0
sub pc, pc, #4
5.0 Intel XScale
Order Number: 316847; Revision:
®
Technology Errata Descriptions
December 2008
005US