NHIXP430AC Intel, NHIXP430AC Datasheet - Page 12

• Manufacturer Part Number: NHIXP430AC
• Manufacturer: Intel

Specifications of NHIXP430AC

• Core Operating Frequency: 400MHz
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

5.
Problem:
Implication:
Workaround:
Status:
6.
Problem:
Implication:
Workaround:
Status:
7.
Problem:
Implication:
Workaround:
Status:
8.
Workaround:
Implication:
Intel
Specification Update
12
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IXP43X Product Line of Network Processors
Intel XScale
If an exception occurs in thumb mode and a non-branch instruction is executed at the
corresponding exception vector, that instruction may execute twice. Instructions
located at exception vectors must be branch instructions that go to the appropriate
handler, but the ARM architecture allows the FIQ handler to be placed directly at the
FIQ vector (0x0000001c/0xffff001c) without requiring a branch. Because of this
condition, the first instruction of such an FIQ handler may be executed twice if it is not
a branch instruction.
Instructions may be executed twice if an exception occurs in thumb mode and if it is a
non-branch instruction.
If a no-op is placed at the beginning of the FIQ handler, the no-op will execute twice
and there will not be any incorrect behavior. If a branch instruction is placed at the
beginning of the handler, it will not be executed twice.
No Fix.
EX_IOWAIT_N Timing
There are two problems with the functionality of the expansion bus IOWAIT protocol. If
both T2 and T3 are programmed to be 0 (normal timing), the expansion bus controller
will not extend the T3 data state as described in Section 12.4.1.5 “Using I/O Wait” on
page 572, of the Intel
- Rev. 001 (April 2007). This occurs because there is a synchronizer on the
EX_IOWAIT_N signal that causes the expansion bus controller to transition to the T4
state before the EX_IOWAIT_N is detected.
Additionally, the Intel
states that the expansion bus controller will transition to the T4 state upon the de-
assertion of EX_IOWAIT_N. The expansion bus controller does not do this — instead it
waits for the T3 count to expire before proceeding to T4.
The expansion bus will not extend the T3 data state as shown in Figure 141 of the
Intel
2007).
To avoid unexpected timing issues, T2 or T3 must be programmed to non-zero values
and assurances made that EX_IOWAIT_N is asserted at least three cycles before the
deasserting edge of EX_RD_N. Additionally, the extended wait states will not be
changed after the deassertion of EX_IOWAIT_N.
No Fix.
Ethernet Coprocessors — Ethernet Pad Enable Overrides Append FCS
The Intel
that is configured by the Intel
via the Ethernet Transmit Control Registers to either append or not append the FCS on
the transmitted Ethernet frames. When the frame payload size is less than 60 bytes,
the Pad Enable control bit has priority over the Append FCS control bit on whether or
not the FCS is appended on a frame.
When the frame payload size is less than 60 bytes, the FCS will be appended to the
Transmit frames even though the Append FCS control bit is not set because the Pad
Enable control bit overrides the Append FCS control bit.
None.
No Fix.
Ethernet Coprocessors — Length Errors on Received Frames
The Intel
that is configured by the Intel
indicate length error on received frames only when stripping of pad bytes from the
received frame is enabled.
Length errors on received frames when pad stripping (Receive Control 1 Register,
bit-1) is disabled will not be indicated to the NPE software when it reads the Receive
status. When pad stripping is enabled, length error indicates that the packet length is
®
IXP43X Product Line of Network Processors Developer’s Manual - Rev. 001 (April
®
®
IXP43X Product Line of Network Processors has an Ethernet coprocessor
IXP43X Product Line of Network Processors has an Ethernet coprocessor
®
Processor Non-Branch Instruction in Vector Table
®
®
IXP43X Product Line of Network Processors Developer’s Manual
IXP43X Product Line of Network Processors Developer’s Manual
®
IXP400 Software. The coprocessor can be programmed
®
IXP400 Software. The Ethernet coprocessor can
4.0 Non-Intel XScale
Order Number: 316847; Revision:
®
Technology Errata Descriptions
December 2008
005US