GS8162Z36BGD-200 GSI TECHNOLOGY, GS8162Z36BGD-200 Datasheet

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GS8162Z36BGD-200

Manufacturer Part Number
GS8162Z36BGD-200
Description
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS8162Z36BGD-200

Density
18Mb
Access Time (max)
6.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
153.8MHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
19b
Package Type
FBGA
Operating Temp Range
0C to 70C
Number Of Ports
4
Supply Current
205mA
Operating Supply Voltage (min)
2.3/3V
Operating Supply Voltage (max)
2.7/3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
165
Word Size
36b
Number Of Words
512K
Lead Free Status / Rohs Status
Compliant
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump and 165-bump BGA packages
• RoHS-compliant 119-bump and 165-bump BGA packages
Functional Description
The GS8162Z18/36B(B/D) is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.06a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
available
Flow Through
Pipeline
3-1-1-1
2-1-1-1
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
Curr
Curr
Curr
Curr
tCycle
tCycle
Parameter Synopsis
t
t
KQ
KQ
(x18)
(x36)
(x18)
(x36)
1/33
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z18/36B(B/D) may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162Z18/36B(B/D) is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
-250
295
345
225
255
2.5
4.0
5.5
5.5
-200
245
285
200
220
3.0
5.0
6.5
6.5
-150
200
225
185
205
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
GS8162Z18/36B(B/D)
© 2004, GSI Technology
250 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS8162Z36BGD-200

GS8162Z36BGD-200 Summary of contents

Page 1

... KQ 5.5 tCycle 225 Curr (x18) 255 Curr (x36) 1/33 GS8162Z18/36B(B/D) 250 MHz–150 MHz 3.3 V I/O -150 Unit 3.0 3 5.0 6.7 245 200 mA mA 285 225 6.5 7.5 ns 6.5 7.5 ns 200 185 mA mA 220 205 © 2004, GSI Technology DD ...

Page 2

... CKE ADV TDI A1 TDO A A TMS A0 TCK A 2/33 GS8162Z18/36B(B/D) (Package DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2004, GSI Technology ...

Page 3

... TDI A1 TDO A A TMS A0 TCK A 3/33 GS8162Z18/36B(B/D) (Package DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2004, GSI Technology ...

Page 4

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com DDQ ADV DQP DDQ DDQ CKE V D DDQ DQP LBO TMS TDI TCK TDO DDQ 4/33 GS8162Z18/36B(B/ DDQ DQP DDQ DDQ DDQ DQP DDQ © 2004, GSI Technology ...

Page 5

... T U Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com DDQ ADV DDQ DDQ CKE V B DDQ LBO TMS TDI TCK TDO DDQ 5/33 GS8162Z18/36B(B/ DDQ DDQ DDQ DDQ DDQ © 2004, GSI Technology ...

Page 6

... Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply Must Connect High (165 BGA only) 6/33 GS8162Z18/36B(B/D) I/Os; active low D BPR1999.05.18 © 2004, GSI Technology ...

Page 7

... Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com and B ) determine which bytes will be written. All or none may be activated 7/33 GS8162Z18/36B(B/ and E ). Deassertion of any one of the Enable 2, 3 © 2004, GSI Technology ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. External L Next L External L Next L External L None L Next L Next L None L None L None L None L None Current L 8/33 GS8162Z18/36B(B/ High High High High-Z 1,2,3, High High High High High © 2004, GSI Technology Notes 1,10 2 1,2, 1,3, ...

Page 9

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow through Read/Write Control State Diagram 9/33 GS8162Z18/36B(B/D) New Write Burst Write B D n+3 ƒ ƒ © 2004, GSI Technology ...

Page 10

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 10/33 GS8162Z18/36B(B/D) Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2004, GSI Technology ...

Page 11

... Pipeline and Flow Through Read Write Control State Diagram 11/33 GS8162Z18/36B(B/ Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2004, GSI Technology ...

Page 12

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pin State Function Name L Linear Burst LBO H Interleaved Burst L Flow Through Pipeline Active ZZ Standby High Drive (Low Impedance Low Drive (High Impedance) 12/33 GS8162Z18/36B(B/ © 2004, GSI Technology ...

Page 13

... Note: The burst counter wraps to initial state on the 5th clock. Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH 13/33 GS8162Z18/36B(B/D) A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 2. The duration of SB tZZR pipelined parts and V DD DDQ © 2004, GSI Technology SS ...

Page 14

... Min. Typ. Max. 3.0 3.3 3.6 2.3 2.5 2.7 3.0 3.3 3.6 2.3 2.5 2.7 Typ. Max. Unit V + 0.3 V — DD — 0 0.3 V — DDQ — 0.8 V © 2004, GSI Technology Unit Unit Notes — — ...

Page 15

... Overshoot Measurement and Timing Symbol Test conditions I/O OUT 15/33 GS8162Z18/36B(B/D) Typ. Max. Unit V + 0.3 V — DD 0.3*V V — 0.3 — V DDQ 0.3*V V — DD Typ. Max. Unit   50% tKC DD IL Typ. Max. Unit © 2004, GSI Technology Notes — — Notes 2 2 ...

Page 16

... V V I Output Disable –8 mA, V OH2 –8 mA, V OH3 16/33 GS8162Z18/36B(B/D) * Min –  V – V –  V –100 V – –1 uA OUT DD = 2.375 V 1.7 V DDQ = 3.135 V 2.4 V DDQ — © 2004, GSI Technology Max 100 — — 0.4 V ...

Page 17

... DD3 DD2 DDQ3 DDQ2 17/33 GS8162Z18/36B(B/D) -200 -150 –40 0 –40 0 – 85°C 70°C 85°C 70°C 85°C 315 255 265 205 215 245 205 215 190 200 285 230 240 185 195 225 190 200 175 185 © 2004, GSI Technology Unit ...

Page 18

... GSI Technology ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Suspend Read C Write D Write No-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 19/33 GS8162Z18/36B(B/D) Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2004, GSI Technology ...

Page 20

... Flow Through Mode Timing (NBT) Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 20/33 GS8162Z18/36B(B/D) Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology tKQX D(G) ...

Page 21

... Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com TDO should be left unconnected Description 21/33 GS8162Z18/36B(B/D) . The JTAG output DD © 2004, GSI Technology ...

Page 22

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 22/33 GS8162Z18/36B(B/D) · · TDO © 2004, GSI Technology ...

Page 23

... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Not Used Configuration 23/33 GS8162Z18/36B(B/D) GSI Technology I/O JEDEC Vendor ID Code © 2004, GSI Technology ...

Page 24

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 24/33 GS8162Z18/36B(B/D) 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2004, GSI Technology ...

Page 25

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 25/33 GS8162Z18/36B(B/D) © 2004, GSI Technology ...

Page 26

... Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Conditions V – DDQ V /2 DDQ Description 26/33 GS8162Z18/36B(B/D) JTAG Port AC Test Load 50 * 30pF V /2 DDQ * Distributed Test Jig Capacitance Notes © 2004, GSI Technology ...

Page 27

... GS8162Z18/36B(B/D) Min. Max. Unit Notes V +0.3 2.0 V DD3 –0.3 0 +0.3 V DD2 DD2 0 –0.3 V DD2 1 uA –300 –1 100 –1 1.7 — V 0.4 V — V – 100 mV V — DDQ — 100 mV V tTKL tTKL © 2004, GSI Technology ...

Page 28

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Min Max Unit — — — — — — 28/33 GS8162Z18/36B(B/D) © 2004, GSI Technology ...

Page 29

... Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) 29/33 GS8162Z18/36B(B/ 1.27 © 2004, GSI Technology ...

Page 30

... Package Dimensions—165-Bump FPBGA (Package D) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 30/33 GS8162Z18/36B(B/D) A1 CORNER 1.0 © 2004, GSI Technology ...

Page 31

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.06a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 32

... GS8162Z18BGD-200I GS8162Z18BGD-150I 512K x 36 GS8162Z36BGD-250I 512K x 36 GS8162Z36BGD-200I 512K x 36 GS8162Z36BGD-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36BB-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 33

... Added MCH (Must Connect High) to pin description • Rev1.05a: updated coplanarity for 119, 165 BGA Content mechanical;removed Status column from Ordering Information table. • Updated for MP status Content • Rev1.06a: removed on-chip parity references. 33/33 GS8162Z18/36B(B/D) © 2004, GSI Technology ...

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