AD5648ARUZ-2 Analog Devices Inc, AD5648ARUZ-2 Datasheet - Page 25

• Manufacturer Part Number: AD5648ARUZ-2
• Description: IC DAC 14BIT OCT 5V REF 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5648ARUZ-2

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Settling Time: 6µs
• Number Of Bits: 14
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 14bit
• Sampling Rate: 95kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 2.7V To 3.6V, 4.5V To 5.5V
• Supply Current: 2mA
• Digital Ic Case: RoHS Compliant
• Number Of Channels: 8
• Resolution: 14b
• Conversion Rate: 95KSPS
• Interface Type: SER 3W SPI QSPI UW
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±8+/- LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Compliant

LDAC FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Synchronous LDAC : After new data is read, the DAC registers
are updated on the falling edge of the 32
can be permanently low or pulsed as in
Asynchronous LDAC : The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software LDAC function by writing to Input
Register n and updating all DAC registers. Command 0011 is
reserved for this software LDAC function.
An LDAC register gives the user extra flexibility and control
over the hardware LDAC pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that this channel’s update
is controlled by the LDAC pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the LDAC pin. It
effectively sees the LDAC pin as being tied low. (See
for the
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 8-bit LDAC
register (DB7 to DB0). The default for each channel is 0, that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC channel is updated regardless of the state of the LDAC
pin. See
during the load
Table 15. LDAC Register
LDAC Bits (DB7 to DB0)
0
1
Table 16. 32-Bit Input Shift Register Contents for LDAC Register Function
MSB
DB31
to
DB28
X
Don’t
cares
LDAC register mode of operation.) This flexibility is
Table 16
DB27
0
Load DAC Register
Command bits (C3 to C0)
LDAC register mode of operation.
for the contents of the input shift register
DB26
1
DB25
1
LDAC Pin
1/0
X—don’t care
DB24
0
Figure 2
nd
DB23
X
SCLK pulse. LDAC
Address bits (A3 to A0)—
.
LDAC Operation
Determined by LDAC pin.
DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.
DB22
X
don’t cares
Table 15
DB21
X
Rev. E | Page 25 of 28
DB20
X
DB19
to
DB8
X
Don’t
cares
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5628/AD5648/
AD5668 should have separate analog and digital sections. If the
AD5628/AD5648/AD5668 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5628/AD5648/AD5668.
The power supply to the AD5628/AD5648/AD5668 should be
bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor has low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 μF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
DB7
DAC
H
DB6
DAC
G
Setting LDAC bit to 1 overrides LDAC pin
DB5
DAC
F
AD5628/AD5648/AD5668
DB4
DAC
E
DB3
DAC
D
DB2
DAC
C
DB1
DAC
B
LSB
DB0
DAC
A