AD5648ARUZ-2 Analog Devices Inc, AD5648ARUZ-2 Datasheet - Page 21

• Manufacturer Part Number: AD5648ARUZ-2
• Description: IC DAC 14BIT OCT 5V REF 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5648ARUZ-2

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Settling Time: 6µs
• Number Of Bits: 14
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 14bit
• Sampling Rate: 95kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 2.7V To 3.6V, 4.5V To 5.5V
• Supply Current: 2mA
• Digital Ic Case: RoHS Compliant
• Number Of Channels: 8
• Resolution: 14b
• Conversion Rate: 95KSPS
• Interface Type: SER 3W SPI QSPI UW
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±8+/- LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Compliant

OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
amplifier is capable of driving a load of 2 kΩ in parallel with
200 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 31 and Figure 32. The slew rate
is 1.5 V/μs with a ¼ to ¾ scale settling time of 7 μs.
SERIAL INTERFACE
The AD5628/AD5648/AD5668 have a 3-wire serial interface
( SYNC , SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 2
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5628/AD5648/AD5668 compatible
with high speed DSPs. On the 32
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
the mode of operation. At this stage, the SYNC line can be kept
low or be brought high. In either case, it must be brought high
for a minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. SYNC
should be idled low between write sequences for even lower
power operation of the part. As is mentioned previously,
however, SYNC must be brought high again just before the next
write sequence.
for a timing diagram of a typical write sequence.
nd
falling clock edge, the last
DD
. The
Rev. E | Page 21 of 28
Table 7. Command Definitions
C3
0
0
0
0
0
0
0
0
1
1
–
1
Table 8. Address Commands
A3
0
0
0
0
0
0
0
0
1
Command
C2
0
0
0
0
1
1
1
1
0
0
–
1
A2
0
0
0
0
1
1
1
1
1
Address (n)
C1
0
0
1
1
0
0
1
1
0
0
–
1
A1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
–
1
C0
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up internal REF register
Reserved
Reserved
Reserved
A0
0
1
0
1
0
1
0
1
1
AD5628/AD5648/AD5668
Selected DAC Channel
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs