CS4365-DQZR Cirrus Logic Inc, CS4365-DQZR Datasheet - Page 35

• Manufacturer Part Number: CS4365-DQZR
• Description: IC DAC 6CH 114DB 192KHZ 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4365-DQZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 6
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 390mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: 598-1779 - EVALUATION BOARD FOR CS4365
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

DS670F2
6.2.3 PCM/DSD Selection (DSD/PCM)
6.2.4 DAC Pair Disable (DACx_DIS)
6.2.5 Power Down (PDN)
6.3
6.3.1 Digital Interface Format (DIF)
DIF3
0
7
PCM Control (address 03h)
Default = 0
0 - PCM
1 - DSD
Function:
This function selects DSD or PCM Mode. The appropriate data and clocks should be present before
changing modes, or else MUTE should be selected.
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
Default = 0000 - Format 0 (Left-Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether
PCM or DSD Mode is selected.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in
Note:
to ensure proper switching from one mode to another.
While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
DIF2
6
0
DIF1
5
0
DIF0
0
4
Figures 8
Reserved
3
0
through 15.
Reserved
2
0
FM1
1
1
CS4365
FM0
0
1
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