AD5762RCSUZ Analog Devices Inc, AD5762RCSUZ Datasheet - Page 22

• Manufacturer Part Number: AD5762RCSUZ
• Description: IC DAC DUAL 16BIT 1LSB 32-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5762RCSUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 180mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 84.6MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 4.25mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5762R
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines. The first falling edge of SYNC
starts the write cycle. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 24 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructed. Each device in
the system requires 24 clock pulses. Therefore, the total number
of clock cycles must equal 24n, where n is the total number of
AD5762R devices in the chain. When the serial transfer to all
devices is complete, SYNC is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11*
MISO
Figure 40. Daisy-Chaining the AD5762R
MOSI
SCK
PC7
PC6
SDIN
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
AD5762R*
AD5762R*
AD5762R*
SDIN
SDIN
SDO
SDO
SDO
Rev. A | Page 22 of 32
A continuous SCLK source can be used only if SYNC is held low
for the correct number of clock cycles. In gated clock mode, a
burst clock containing the exact number of clock cycles must be
used, and SYNC must be taken high after the final clock to latch
the data.
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the SDO
disable bit; this bit is cleared by default. Readback mode is
invoked by setting the R/ W bit = 1 in the serial input register
write. With R/ W = 1, Bit A2 to Bit A0, in association with Bit
REG2, Bit REG1, and Bit REG0, select the register to be read.
The remaining data bits in the write sequence are don’t care.
During the next SPI write, the data appearing on the SDO output
contains the data from the previously addressed register. For a
read of a single register, the NOP command can be used in clocking
out the data from the selected register on SDO. The readback
diagram in
to read back the fine gain register of Channel A on the AD5762R,
implement the following sequence:
1.
2.
SIMULTANEOUS UPDATING VIA LDAC
Depending on the status of both SYNC and LDAC , and after
data has been transferred into the input register of the DACs,
there are two ways to update the DAC registers and DAC outputs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC .
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are updated by
taking LDAC low any time after SYNC has been taken high.
The update then occurs on the falling edge of LDAC .
Write 0xA0XXXX to the input register. This write configures
the AD5762R for read mode with the fine gain register of
Channel A selected. Note that all of the data bits, DB15 to
DB0, are don’t care.
Follow with a second write: an NOP condition, 0x00XXXX.
During this write, the data from the fine gain register is
clocked out on the SDO line; that is, data clocked out contains
the data from the fine gain register in Bit DB5 to Bit DB0.
Figure 4
shows the readback sequence. For example,