AD5762RCSUZ Analog Devices Inc, AD5762RCSUZ Datasheet - Page 12

• Manufacturer Part Number: AD5762RCSUZ
• Description: IC DAC DUAL 16BIT 1LSB 32-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5762RCSUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 180mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 84.6MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 4.25mA
• Digital Ic Case Style: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5762R
Pin No.
22
23
24
25
26
27
28
29
32
1
Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Mnemonic
VOUTA
NC
NC
REFA
REFB
REFOUT
REFGND
TEMP
BIN/2sCOMP
Description
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier
is capable of directly driving a 10 kΩ, 200 pF load.
Do not connect to this pin.
Do not connect to this pin.
External Reference Voltage. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage.
REFA = 5 V for specified performance.
External Reference Voltage. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage.
REFB = 5 V for specified performance.
Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ±
3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C.
Reference Ground Return for the Reference Generator and Buffers.
This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die
temperature; variation with temperature is 5 mV/°C.
This pin determines the DAC coding. This pin should be hardwired to either DV
DV
Table 8).
CC
, input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement (see
Rev. A | Page 12 of 32
CC
or DGND. When hardwired to