AD7392ARZ Analog Devices Inc, AD7392ARZ Datasheet - Page 13

• Manufacturer Part Number: AD7392ARZ
• Description: IC DAC 12BIT PARALLEL 3V 20-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7392ARZ

• Data Interface: Parallel
• Settling Time: 60µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 500µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 17kSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analogue: 2.7V To 5.5V
• Supply Current: 55µA
• Digital Ic Case Style: SOIC
• Number Of Channels: 1
• Resolution: 12b
• Conversion Rate: 17KSPS
• Interface Type: Parallel
• Single Supply Voltage (typ): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

POWER SUPPLY
The very low power consumption of the AD7392/AD7393 is
a direct result of a circuit design that optimizes the CBCMOS
process. By using the low power characteristics of CMOS for the
logic and the low noise, tight-matching of the complementary
bipolar transistors, excellent analog accuracy is achieved. One
advantage of the rail-to-rail output amplifiers used in the AD7392/
AD7393 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 2.7 V to 5.5 V.
Whether or not a separate power supply trace is available, gen-
erous supply bypassing reduces supply line induced errors. Local
supply bypassing, consisting of a 10 μF tantalum electrolytic in
parallel with a 0.1 μF ceramic capacitor, is recommended for all
applications (see Figure 29).
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure that allows logic input voltages to exceed the V
voltage (see Figure 30). This feature is useful if the user is driving
one or more of the digital inputs with a 5 V CMOS logic input
voltage level while operating the AD7392/AD7393 on a 3 V
power supply. If this interface is used, make sure that the V
of the 5 V CMOS meets the V
AD7393 operating at 3 V. See Figure 12 for a graph of digital
logic input threshold vs. operating V
TTL/CMOS
CIRCUITS
LOGIC
POWER SUPPLY
Figure 29. Recommended Supply Bypassing for the AD7392/AD7393
D0 TO D11
* OPTIONAL EXTERNAL
Figure 28. Use Separate Traces to Reduce Power Supply Noise
REFERENCE BYPASS
5V
Figure 30. Equivalent Digital Input ESD Protection
*
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
C
LOGIC
2
3
4
GND
V
DD
IN
SHDN
CS
RS
V
REF
AD7392
AD7393
20
+ 100µF
1kΩ
ELECT.
GND
OR
IL
2.7V TO 5.5V
17, 18
input requirement of the AD7392/
V
DD
1
+ 10µF TO 22µF
DD
TANT.
supply voltage.
19
0.1µF
+
+ 0.1µF
CER.
10µF
DD
V
OUT
supply
5V
5V
RETURN
OL
Rev. C | Page 13 of 20
To minimize power dissipation from input logic levels that
are near the V
Schmitt-trigger design was used that minimizes the input
buffer current consumption compared to traditional CMOS
input stages. Figure 11 is a plot of supply current vs. incremental
input voltage, showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions.
A secondary advantage of this Schmitt trigger is the prevention
of false triggers that would occur with slow moving logic transi-
tions when a standard CMOS logic interface or opto-isolators
are used. Logic inputs D11 to D0, CS , RS , and SHDN all contain
the Schmitt-trigger circuits.
DIGITAL INTERFACE
The AD7392/AD7393 have a parallel data input. A functional
block diagram of the digital section is shown in Figure 31,
while Table 6 contains the truth table for the logic control
inputs. The chip select pin ( CS ) controls loading of data from
the data inputs on Pin D11 to Pin D0. This active low input
places the input register into a transparent state allowing the
data inputs to directly change the DAC ladder values. When
CS returns to logic high within the data setup-and-hold time
specifications, the new value of data in the input register are
latched. See Table 6 for a complete listing of conditions.
Table 6. Control Logic Truth Table
CS
H
L
↑
X
H
1
2
CS
RS
Dx
X = Don’t care.
1
↑ = Positive logic transition.
2
RS
H
H
H
L
↑
1
IH
and V
Figure 31. Digital Control Logic
DAC Register Function
Latched
Transparent
Latched with new data
Loaded with all zeros
Latched all zeros
IL
logic input voltage specifications, a
1 OF 12 LATCHES
DAC REGISTER
AD7392/AD7393
OF THE
TO
INTERNAL
DAC SWITCHES