ADV7125KSTZ140 Analog Devices Inc, ADV7125KSTZ140 Datasheet - Page 8

• Manufacturer Part Number: ADV7125KSTZ140
• Description: IC DAC VIDEO 3-CH 140MHZ 48LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADV7125KSTZ140

• Data Interface: Parallel
• Number Of Bits: 8
• Number Of Converters: 3
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 30mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 8bit
• Sampling Rate: 330MSPS
• Input Channel Type: Parallel
• Supply Current: 67mA
• Digital Ic Case Style: QFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7125
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin Number
1, 2, 14, 15, 25,
26, 39, 40
3 to 10, 16 to
23, 41 to 48
11
12
13, 29, 30
24
33, 31, 27
34, 32, 28
35
36
Mnemonic
GND
G0 to G7,
B0 to B7,
R0 to R7
BLANK
SYNC
V
CLOCK
IOR, IOG, IOB
IOR, IOG, IOB
COMP
V
AA
REF
Description
Ground. All GND pins must be connected.
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be
connected to either the regular printed circuit board (PCB) power or ground plane.
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of
CLOCK. While BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored.
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a
40 IRE current source. This is internally connected to the IOG analog output. SYNC does not override
any other control or data input; therefore, it should only be asserted during the blanking interval.
SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel,
the SYNC input should be tied to Logic 0.
Analog Power Supply (5 V ± 5%). All V
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7, SYNC,
and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK
should be driven by a dedicated TTL buffer.
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω
load. If the complementary outputs are not required, these outputs should be tied to ground.
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output
loads whether or not they are all being used.
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic
capacitor must be connected between COMP and V
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
BLANK
NOTES
1. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE
SYNC
GND
GND
CONNECTED TO GND.
G0
G1
G2
G3
G4
G5
G6
G7
10
12
11
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 3. Pin Configuration
Rev. C | Page 8 of 16
(Not to Scale)
ADV7125
TOP VIEW
AA
pins on the ADV7125 must be connected.
36
35
34
33
32
31
30
29
28
27
26
25
AA
V
COMP
IOR
IOR
IOG
IOG
V
V
IOB
IOB
GND
GND
REF
AA
AA
.