ADV7125KSTZ140 Analog Devices Inc, ADV7125KSTZ140 Datasheet - Page 13

• Manufacturer Part Number: ADV7125KSTZ140
• Description: IC DAC VIDEO 3-CH 140MHZ 48LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADV7125KSTZ140

• Data Interface: Parallel
• Number Of Bits: 8
• Number Of Converters: 3
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 30mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 8bit
• Sampling Rate: 330MSPS
• Input Channel Type: Parallel
• Supply Current: 67mA
• Digital Ic Case Style: QFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 5 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of
Figure 6. As well as the gray scale levels (black level to white
level), Figure 5 also shows the contributions of SYNC and
BLANK for the ADV7125. These control inputs add appro-
priately weighted currents to the analog outputs, producing
the specific output level requirements for video applications.
Table 7
output levels.
GRAY SCALE OPERATION
The ADV7125 can be used for standalone, gray scale (mono-
chrome) or composite video applications (that is, only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to Logic 0. The
unused analog outputs should be terminated with the same load
as that for the used channel, that is, if the red channel is used
and IOR is terminated with a doubly terminated 75 Ω load
(37.5 Ω), IOB and IOG should be terminated with 37.5 Ω
resistors (see Figure 8).
VIDEO OUTPUT BUFFERS
The ADV7125 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in the
Analog Outputs section and illustrated in Figure 9. However,
in some applications, it may be required to drive long transmis-
sion line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able
to supply sufficient current over the complete output voltage
swing. Analog Devices produces a range of suitable op amps for
such applications. These include the AD843, AD844, AD847,
and
applications (80 MHz), the
information on line driver buffering circuits is given in the
relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
Figure 8. Input and Output Connections for Standalone Gray Scale or
AD848
OUTPUT
details how the
VIDEO
series of monolithic op amps. In very high frequency
R0
R7
G0
G7
B0
B7
ADV7125
SYNC and BLANK inputs modify the
Composite Video
AD8061
GND
IOG
IOR
IOB
is recommended. More
37.5Ω
37.5Ω
DOUBLY
TERMINATED
75Ω LOAD
Rev. C | Page 13 of 16
PCB LAYOUT CONSIDERATIONS
The ADV7125 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7125, it is imperative
that great care be given to the PCB layout. Figure 10 shows a
recommended connection diagram for the ADV7125.
The layout should be optimized for lowest noise on the
ADV7125 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of V
to minimize inductive ringing.
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 10). Optimum
performance is achieved by using 0.1 μF and 0.01 μF ceramic
capacitors. Individually decouple each V
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7125
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3-
terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7125 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7125 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (V
analog power plane.
TERMINATION)
IOR, IOG, IOB
DACs
(SOURCE
Z
S
= 75Ω
Z
2
2
3
Figure 9. AD848 As an Output Buffer
AD848
+V
–V
4
6
S
S
Z
1
0.1µF
0.1µF
7
GAIN (G) = 1 +
75Ω
Z
(CABLE)
AA
0
CC
Z
Z
= 75Ω
pin to ground by
1
2
) and not to the
AA
and GND pins
ADV7125
Z
(MONITOR)
L
= 75Ω