X9418WV24Z-2.7 Intersil, X9418WV24Z-2.7 Datasheet - Page 9

• Manufacturer Part Number: X9418WV24Z-2.7
• Description: IC XDCP DUAL 64TAP 10K 24-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9418WV24Z-2.7

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Wiper Counter Register, (6-Bit), Volatile
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
XFR Data Register (DR) to Wiper Counter Register (WCR)
R
R
S
A
R
S
A
R
S
A
R
S
T
A
T
S
T
A
T
T
T
T
T
T
T
(MSB)
WP5
V
device type
device type
0 1 0 1
0 1 0 1
device type
0 1 0 1
device type
0 1 0 1
device type
0 1 0 1
identifier
identifier
identifier
identifier
identifier
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
WP4
V
A
3
A
3
addresses
A
A
A
addresses
3
3
3
addresses
addresses
addresses
device
device
device
device
device
A
2
A
2
A
A
A
2
WP3
2
2
V
A
1
A
1
A
A
A
1
1
1
A
0
A
0
A
A
A
0
0
0
9
S
A
C
K
C
S
A
K
WP2
C
C
S
A
C
K
S
A
K
S
A
K
V
1 1 0 0
1 1 0 1
instruction
instruction
1 0 1 1
1 0 0 1 0 0 0
1 0 1 0 0 0 0
instruction
instruction
instruction
opcode
opcode
opcode
opcode
opcode
WP1
V
R
DR and WCR
1
R
DR and WCR
1
DR and WCR
R
1
addresses
addresses
addresses
addresses
(LSB)
WP0
addresses
R
R
0
WCR
WCR
0
V
R
0
0
0 P0
0
X9418
P
P
0
0
P
0
P
0
S
A
C
K
S
A
C
K
S
A
C
K
S
A
C
K
S
A
C
K
0 0
0 0
(sent by master on SDA)
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
O
S
T
P
(sent by slave on SDA)
(sent by master on SDA)
0 0
0 0
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
(sent by slave on SDA)
wiper position/data
wiper position/data
wiper position
wiper position
W
W
P
P
5
5
W
P
5
W
P
5
W
W
P
P
4
4
W
P
4
W
P
4
W
W
P
P
3
3
W
P
3
W
P
3
W
W
P
P
2
2
W
P
2
W
P
2
W
W
P
P
1
1
W
P
1
W
P
1
W
W
P
P
0
0
W
P
0
W
P
0
M
A
C
K
S
A
C
K
C
S
A
K
M
A
C
K
O
O
S
T
P
S
T
P
O
S
T
P
O
S
P
T
HIGH-VOLTAGE
WRITE CYCLE
October 12, 2006
FN8194.3