ISL22326WFV14Z Intersil, ISL22326WFV14Z Datasheet - Page 4

• Manufacturer Part Number: ISL22326WFV14Z
• Description: IC POT DGTL 128TP LN LP 14-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22326WFV14Z

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating Specifications
Analog Specifications
RESISTOR MODE (Measurements between R
SYMBOL
VccRamp
(Note 19)
(Note 19)
t
SYMBOL
(Note 15)
(Note 14)
(Note 13)
(Note 16)
R
ShdnRec
I
Roffset
LkgDig
RDNL
t
I
I
Vpor
RINL
MATCH
WRT
CC1
CC2
I
I
SB
SD
V
Write/Read)
V
Write/Read)
V
V
Leakage Current, at Pins A0, A1, A2,
SHDN, SDA and SCL
DCP Wiper Response Time
DCP Recall Time from Shutdown
Mode
Power-on Recall Voltage
V
Integral Non-linearity
Differential Non-linearity
Offset
DCP to DCP Matching
CC
CC
CC
CC
CC
Supply Current (Volatile
Supply Current (Non-volatile
Current (Standby)
Current (Shutdown)
Ramp Rate
PARAMETER
PARAMETER
Over recommended operating conditions, unless otherwise stated. (Continued)
4
Over the recommended operating conditions, unless otherwise specified.
W
i and R
f
read and write states)
f
read and write states)
V
standby state
V
standby state
V
standby state
V
standby state
V
standby state
V
standby state
V
standby state
V
standby state
Voltage at pin from GND to V
SCL falling edge of last bit of DCP data byte
to wiper new position
From rising edge of SHDN signal to wiper
stored position and RH connection
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
Minimum V
occurs
SCL
SCL
DCP register set between 10h and 7Fh;
monotonic over all tap positions
DCP register set between 10h and 7Fh;
monotonic over all tap positions, W option
DCP register set between 10h and 7Fh;
monotonic over all tap positions, U option
W option
U option
Any two DCPs at the same tap position with
the same terminal voltages
CC
CC
CC
CC
CC
CC
CC
CC
L
i with R
= 400kHz; SDA = Open; (for I
= 400kHz; SDA = Open; (for I
= +5.5V @ +85°C, I
= +5.5V @ +125°C, I
= +3.6V @ +85°C, I
= +3.6V @ +125°C, I
= +5.5V @ +85°C, I
= +5.5V @ +125°C, I
= +3.6V @ +85°C, I
= +3.6V @ +125°C, I
H
CC
ISL22326
TEST CONDITIONS
TEST CONDITIONS
i not connected, or between R
at which memory recall
2
2
2
2
C interface in
C interface in
C interface in
C interface in
2
2
2
2
C interface in
C interface in
C interface in
C interface in
CC
2
2
C, active,
C, active,
W
i and R
(Note 20)
(Note 20)
MIN
2.0
0.2
MIN
-0.5
-1
-1
-1
-2
0
0
H
i with R
(Note 4)
(Note 4)
L
TYP
TYP
1.5
1.5
1.5
0.5
i not connected. i = 0 or 1)
1
(Note 20)
(Note 20)
MAX
MAX
0.5
0.5
2.6
1
1
5
2
2
3
5
7
3
5
3
5
2
4
1
September 8, 2009
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
UNIT
UNIT
V/ms
FN6176.2
MI
MI
MI
MI
MI
MI
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
µs
µs
V