LTC1290BIJ Linear Technology, LTC1290BIJ Datasheet - Page 20

• Manufacturer Part Number: LTC1290BIJ
• Description: 12-BIT SERIAL I/O ADC W/8 CH MUX
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1290BIJ

• Resolution (bits): 12 b
• Sampling Rate (per Second): 50k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Dual ±
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1290
A
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (t
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing R
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 2µs, R
and C1 < 20pF will provide adequate settling.
20
PPLICATI
V
V
IN
IN
“+” INPUT
“–” INPUT
+
–
SCLK
ACLK
R
CS
R
SOURCE
SOURCE
Figure 9. Analog Input Equivalent Circuit
+
–
O
SOURCE
1
U
C1
INPUT
INPUT
C2
SMPL
“+”
“–”
S
MUX ADDRESS
SHIFTED IN
2
I FOR ATIO
, see Figure 10). The sample
+
U
and C1 will improve the input
3
4TH SCLK
LAST SCLK
R
W
ON
Figure 10. “+” and “–” Input Settling Windows
SAMPLE
= 500Ω
4
SOURCE
LTC1290
C
100pF
LTC1290 F09
DURING THIS TIME
IN
• • •
• • •
• • •
MUST SETTLE
U
=
“+” INPUT
t
SMPL
+
< 1k
HOLD
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
R
input source resistance must be used, the time allowed for
settling can be extended by using a slower ACLK fre-
quency. At the maximum ACLK rate of 4MHz, R
< 250
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommo-
date slower op amps. Most op amps including the LT1797,
LT1800 and LT1812 single supply op amps can be made
to settle well even with the minimum settling windows of
2µs (“+” input) and 1µs (“–” input) which occur at the
“–” INPUT MUST SETTLE
SOURCE
DURING THIS TIME
1
1ST BIT TEST
Ω
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORD LENGTH)
2
and C2 < 20pF will provide adequate settling.
–
3
and C2 will improve settling time. If large “–”
4
• • •
1290 • F10
SOURCE
1290fe
–