LTC1290BIJ Linear Technology, LTC1290BIJ Datasheet - Page 10

• Manufacturer Part Number: LTC1290BIJ
• Description: 12-BIT SERIAL I/O ADC W/8 CH MUX
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1290BIJ

• Resolution (bits): 12 b
• Sampling Rate (per Second): 50k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Dual ±
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1290
A
The LTC1290 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1290 communicates with microprocessors and
other external circuitry via a synchronous, full duplex,
four-wire serial interface (see Operating Sequence). The
shift clock (SCLK) synchronizes the data transfer with
each bit being transmitted on the falling SCLK edge and
captured on the rising SCLK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the D
for the next conversion. Simultaneously, the result of the
10
D OUT
SCLK
PPLICATI
converter
D IN
CS
1
2
O
SHIFT CONFIGURATION
IN
3
U
input which configures the LTC1290
WORD IN
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
S
4
5
I FOR ATIO
U
6
7
8
W
t CYC
t SMPL
9
10
11
U
12
DON’T CARE
Operating Sequence
DON’T CARE
t CONV
previous conversion is output on the D
of the data exchange the requested conversion begins and
CS should be brought high. After t
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting it.
Input Data Word
The LTC1290 8-bit data word is clocked into the D
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the D
until the next CS cycle. The eight bits of the input word are
defined as follows:
D
D
IN
OUT
SGL/
DIFF
D
D
IN
OUT
TRANSFER
WORD 1
DATA
B11 B10 B9
(SB)
ODD/
SIGN
MUX ADDRESS
WORD 0
SELECT
CONVERSION
1
t
NEW CONFIGURATION WORD IN
CONV
A/D
B8
SHIFT A/D RESULT OUT AND
SELECT
B7 B6
0
D
D
IN
OUT
TRANSFER
WORD 2
UNIPOLAR/
DATA
BIPOLAR
WORD 1
B5
UNI
B4
CONV
IN
MSB-FIRST/
CONVERSION
LSB-FIRST
B3
pin are then ignored
MSBF
OUT
t
, the conversion is
CONV
A/D
B2
line. At the end
B1
WL1
D
D
IN
OUT
B0
LENGTH
WORD
WORD 3
WORD 2
IN
LTC1290 • AI03
LTC1290 • AI01
LTC1290 • AI02
input
WL0
1290fe