LTC1292CCN8#PBF Linear Technology, LTC1292CCN8#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC1292CCN8#PBF
• Description: IC DATA ACQ SYSTEM 12BIT 8-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1292CCN8#PBF

• Resolution (bits): 12 b
• Sampling Rate (per Second): 60k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC1292/LTC1297
A
the MPU. The data is right-justified in the two memory
locations (Figure 2). This was made possible by delaying
the falling edge of CS till after the second CLK. ANDing the
first byte with 0F
This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
MC68HC11 CODE for LTC1292 Interface
LABEL MNEMONIC
LOOP
10
PPLICATI
D
RECEIVED WORD
CLK
OUT
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDX
LDAB
LDAA
STAA
NOP
CS
ANALOG
INPUTS
MPU
O
HEX
OPERAND
#$50
$1028
#$1B
$1009
#$00
$50
#$1000
#$00
$50
$102A
U
?
clears the four most significant bits.
S
Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
0
LTC1292
I FOR ATIO
U
B11
B11
D
COMMENTS
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DUMMY DIN WORD INTO
ACC A
LOAD DUMMY DIN DATA INTO $50
LOAD INDEX REGISTER X WITH
$1000
LOAD ACC B WITH $00
LOAD DUMMY DIN INTO ACC A
FROM $50
LOAD DUMMY DIN INTO SPI,
START SCK
DELAY CS FALL TIME TO RIGHT
JUSTIFY DATA
CLK
OUT
1ST TRANSFER
CS
B10
B10
Figure 3. Data Exchange Between LTC1297 and MC68HC11
BYTE 1
B9
B9
W
B8
B8
SCK
DO
MISO
MC68HC11
B7
B7
U
B6
B6
LOCATION #61
LOCATION #62
B5
For the LTC1297 (Figure 3) a delay must be introduced to
accommodate the setup time, t
D
clocks B11 through B6 of the A/D conversion result into
the processor. The second 8-bit transfer clocks the re-
maining bits B5 through B0 into the MPU. Note B1 and B2
from the LSB-first data word have also been clocked in.
LABEL MNEMONIC
IN
B5
word is sent to the data register. The first 8-bit transfer
D
B4
OUT
B4
B7
O
STAB
NOP
LDAA
LDAA
STAA
STAA
NOPS
BSET
LDAA
LDAA
STAA
JMP
FROM LTC1292 STORED ON MC68HC11 RAM
B3
B3
O
B6
2ND TRANSFER
B2
B2
BYTE 2
B5
O
B1
B1
B4
OPERAND
$08, X
$1029
$102A
$61
$102A
$08,X,$01
$1029
$102A
$62
LOOP
O
MSB
B0
B11
B0
B3
B10
B1
B1
B2
COMMENTS
D0 GOES LOW (CS GOES LOW)
6 NOPS FOR TIMING
CHECK SPI STATUS REG
LOAD LTC1292 MSBs INTO ACC A
STORE MSBs IN $61
LOAD DUMMY DIN INTO SPI,
START SCK
6 NOPS FOR TIMING
D0 GOES HIGH (CS GOES HIGH)
CHECK SPI STATUS REGISTER
LOAD LTC1292 LSBs IN ACC
STORE LSBs IN $62
START NEXT CONVERSION
B2
B2
B9
B1
suCS
B8
B0
B3
, before the dummy
LTC1292/7 F02
BYTE 1
BYTE 2
LTC1292/7 F03
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