604-00026 Parallax Inc, 604-00026 Datasheet - Page 15

• Manufacturer Part Number: 604-00026
• Description: IC ADC 12BIT 8CH MAX1270 24-DIP
• Manufacturer: Parallax Inc

Specifications of 604-00026

• Number Of Bits: 12
• Sampling Rate (per Second): 110k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.07W
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 13a. Internal Reference
Figure 13b. External Reference, Reference at REF
Figure 13c. External Reference, Reference at REFADJ
MAX1270
MAX1271
MAX1270
MAX1271
MAX1270
MAX1271
____________________________________________________________________________________
2.5V
2.5V
2.5V
10k
10k
10k
A
A
A
V
V
V
= 1.638
= 1.638
= 1.638
REFADJ
REFADJ
REFADJ
REF
REF
REF
4.7µF
C
REF
V
4.7µF
C
0.01µF
4.7µF
C
0.01µF
DD
REF
REF
4.096V
Multirange, +5V, 8-Channel,
2.5V
To save power, configure the converter into low-current
shutdown mode between conversions. Two program-
mable power-down modes are available in addition to a
hardware shutdown. Select STBYPD or FULLPD by pro-
gramming PD0 and PD1 in the input control byte
(Table 4). When software power-down is asserted, it
becomes effective only after the end of conversion. For
example, if the control byte contains PD1 = 0, then the
chip will remain powered up. If PD1 = 1, then the chip
will power-down at the end of conversion. In all power-
down modes, the interface remains active and conver-
sion results may be read. Input overvoltage protection
is active in all power-down modes.
The first logical 1 on DIN after CS falls is interpreted as
a start condition, and powers up the MAX1270/
MAX1271 from a software selected STBYPD or FULLPD
condition.
For hardware-controlled power-down (FULLPD), pull
SHDN low. When hardware shutdown is asserted, it
becomes effective immediately, and any conversion in
progress is aborted.
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at REF. This is a “DC” state that does
not degrade after power-down of any duration.
In FULLPD mode, only the bandgap reference is active.
Connect a 33µF capacitor between REF and AGND to
maintain the reference voltage between conversions
and to reduce transients when the buffer is enabled
and disabled. Throughput rates down to 1ksps can be
achieved without allotting extra acquisition time for ref-
erence recovery prior to conversion. This allows con-
version to begin immediately after power-up. If the
discharge of the REF capacitor during FULLPD
exceeds the desired limits for accuracy (less than a
fraction of an LSB), run a STBYPD power-down cycle
prior to starting conversions. Take into account that the
reference buffer recharges the bypass capacitor at an
80mV/ms slew rate, and add 50µs for settling time.
Selecting STBYPD on every conversion automatically
shuts down the MAX1270/MAX1271 after each conver-
sion without requiring any start-up time on the next con-
version.
Serial 12-Bit ADCs
Choosing Power-Down Modes
Power-Down Mode
Auto-Shutdown
7-183