MAX11047ETN+T Maxim Integrated Products, MAX11047ETN+T Datasheet - Page 13

• Manufacturer Part Number: MAX11047ETN+T
• Description: IC ADC 16BIT 250KSPS SAR 56TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX11047ETN+T

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Parallel
• Number Of Converters: 4
• Power Dissipation (max): 2.22W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX11057
(TQFP-EP)
23, 28, 32,
38, 43, 49,
24, 29, 35,
25, 30, 36,
46, 52, 57
45, 51, 56
40,48, 54
8, 22, 59
9, 21, 60
27, 33,
31, 34,
26, 55
53, 58
47, 50
10
11
12
13
14
15
16
17
18
19
20
37
39
1
2
3
4
5
6
7
MAX11058
(TQFP-EP)
23, 28, 32,
38, 43, 49,
24, 29, 35,
25, 30, 36,
46, 52, 57
45, 51, 56
40,48, 54
8, 22, 59
9, 21, 60
27, 33,
53, 58
26, 55
31, 50
PIN
10
11
12
13
14
15
16
17
18
19
20
34
37
1
2
3
4
5
6
7
______________________________________________________________________________________
MAX11059
(TQFP-EP)
23, 28, 32,
38, 43, 49,
24, 29, 35,
25, 30, 36,
46, 52, 57
45, 51, 56
40,48, 54
8, 22, 59
9, 21, 60
27, 33,
53, 58
26, 55
10
11
12
13
14
15
16
17
18
19
20
—
31
34
1
2
3
4
5
6
7
RD C _S E N S E Reference Buffer Sense Feedback. Connect to RDC plane.
DB1/CR3
DB0/CR2
CONVST
AGNDS
NAME
DGND
AGND
SHDN
DV
DB12
DB11
DB10
AV
EOC
RDC
CH0
CH1
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
CR1
CR0
I.C.
DD
DD
Simultaneous-Sampling ADCs
14-Bit Parallel Data Bus Digital Output Bit 12
14-Bit Parallel Data Bus Digital Output Bit 11
14-Bit Parallel Data Bus Digital Output Bit 10
14-Bit Parallel Data Bus Digital Output Bit 9
14-Bit Parallel Data Bus Digital Output Bit 8
14-Bit Parallel Data Bus Digital Output Bit 7
14-Bit Parallel Data Bus Digital Output Bit 6
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input.
14-Bit Parallel Data Bus Digital Output Bit 5
14-Bit Parallel Data Bus Digital Output Bit 4
14-Bit Parallel Data Bus Digital Output Bit 3
14-Bit Parallel Data Bus Digital Output Bit 2
14-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 3
14-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 2
Configuration Register Input Bit 1
Configuration Register Input Bit 0
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
Signal Ground. Connect all AGND and AGNDS inputs together.
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
Analog Ground. Connect all AGND inputs together.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
Internally Connected. Connect to AGND.
Channel 0 Analog Input
Channel 1 Analog Input
4-/6-/8-Channel, 16-/14-Bit,
Pin Description (continued)
FUNCTION
13