MAX11047ETN+T Maxim Integrated Products, MAX11047ETN+T Datasheet - Page 12

• Manufacturer Part Number: MAX11047ETN+T
• Description: IC ADC 16BIT 250KSPS SAR 56TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX11047ETN+T

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Parallel
• Number Of Converters: 4
• Power Dissipation (max): 2.22W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
12
MAX11047
(TQFP-EP)
23, 28, 32,
38, 43, 49,
24, 29, 35,
25, 30, 36,
27, 33, 40,
46, 52, 57
45, 51, 56
31, 34,
53, 58
26, 55
48, 54
47, 50
______________________________________________________________________________________
18
19
20
37
39
41
42
44
61
62
63
64
—
—
—
—
—
MAX11048
(TQFP-EP)
23, 28, 32,
38, 43, 49,
24, 29, 35,
25, 30, 36,
27, 33, 40,
46, 52, 57
45, 51, 56
53, 58
26, 55
48, 54
31, 50
PIN
18
19
20
34
37
41
39
42
44
47
61
62
63
64
—
—
—
MAX11049
(TQFP-EP)
23, 28, 32,
38, 43, 49,
24, 29, 35,
25, 30, 36,
27, 33, 40,
46, 52, 57
45, 51, 56
53, 58
26, 55
48, 54
18
19
20
31
34
41
37
39
42
44
47
50
61
62
63
64
—
—
RD C _S E N S E Reference Buffer Sense Feedback. Connect to RDC plane.
CONVST
AGNDS
NAME
AGND
REFIO
SHDN
AV
DB15
EOC
RDC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
I.C.
WR
RD
CS
EP
DD
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
Signal Ground. Connect all AGND and AGNDS inputs together.
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
Analog Ground. Connect all AGND inputs together.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
Internally Connected. Connect to AGND.
Channel 0 Analog Input
Channel 1 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
Channel 2 Analog Input
Channel 3 Analog Input
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
16-Bit Parallel Data Bus Digital Out Bit 15
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
Pin Description (continued)
FUNCTION