HI7190IB Intersil, HI7190IB Datasheet - Page 19

• Manufacturer Part Number: HI7190IB
• Description: IC ADC 24BIT PROGBL SER 20-SOIC
• Manufacturer: Intersil

Specifications of HI7190IB

• Number Of Bits: 24
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 32.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SDIO
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read cycle,
during the instruction phase of the communication cycle, the
Instruction Byte should be set to a read transfer (R/W = 0).
When reading the serial port, data is driven out of the HI7190
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Detailed Register Descriptions
Data Output Register
The Data Output Register contains 24 bits of converted data.
This register is a read only register.
SCLK
SDO
SCLK
SDIO
SDO
CS
CS
SDIO
SCLK
SDO
CS
I0
I0
I0
I1
I1
I1
IR WRITE PHASE
I2
I2
IR WRITE PHASE
I2
IR WRITE PHASE
THREE-STATE
THREE-STATE
I3
I3
I3
FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW
I4
I4
I4
19
I5
I5
I5
I6
I6
I6
FIGURE 15. DATA WRITE CYCLE, SCLK IDLE HIGH
I7
I7
I7
FIGURE 14. DATA WRITE CYCLE, SCLK IDLE LOW
B0
B0
B0
B1
B1
B1
B2
B2
HI7190
B2
B3
B3
B3
B4
B4
B4
DATA TRANSFER PHASE - TWO-BYTE WRITE
DATA TRANSFER PHASE - TWO-BYTE WRITE
DATA TRANSFER PHASE - TWO-BYTE READ
B5
B5
MSB
D23
D15
D7
15
B5
7
B6
B6
THREE-STATE
B6
B7
D22
D14
D6
22
14
THREE-STATE
6
B7
B7
B8
D21
D13
D5
21
13
5
B8
B8
B9
D20
D12
B9
D4
20
12
4
BYTE 2
BYTE 1
BYTE 0
B9
B10 B11 B12 B13 B14
B10 B11 B12 B13 B14
B10 B11 B12 B13 B14 B15
D19
D11
D3
19
11
3
D18
D10
D2
18
10
2
D17
B15
D9
D1
17
B15
9
1
June 27, 2006
FN3612.10
LSB
D16
D8
D0
16
8