AD7763BSVZ Analog Devices Inc, AD7763BSVZ Datasheet - Page 27

• Manufacturer Part Number: AD7763BSVZ
• Description: IC ADC 24BIT S/D 625KSPS 64-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7763BSVZ

• Data Interface: Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 625k
• Number Of Converters: 1
• Power Dissipation (max): 955.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad
• Resolution (bits): 24bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 2.375V To 2.625V, 3.15V To 5.25V, 4.75V To 5.25V
• Supply Voltage Range -: RoHS Compliant
• Sampling Rate: 625kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTERS
The AD7763 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration,
the low power option, and the control of the differential amplifier. There are also digital gain, offset, and overrange threshold registers.
Writing to these registers involves writing the register address first, followed by a 16-bit data-word. Register addresses, details of individual bits,
and default values are shown here.
CONTROL REGISTER 1—ADDRESS 0X001
Default Value 0x001A
MSB
DL Filt
Table 17.
Bit
15
14
13
12
11
10
9
8 to 5
4
3
2 to 0
1
2
CONTROL REGISTER 2—ADDRESS 0X002
Default Value 0x009B
MSB
0
Table 18.
Bit
3
2
1
0
Bit 15 to Bit 9 are all self-clearing bits.
Only one of these bits can be set in any write operation, because they all determine the contents of the next operation.
Mnemonic
PD
LPWR
1
D1PD
Mnemonic
DL Filt
RD Ovr
RD Gain
RD Off
RD Stat
0
SYNC
FLEN[3:0]
BYP F3
1
DEC[2:0]
RD Ovr
0
1
1
1, 2
1, 2
1, 2
1, 2
RD Gain
Comment
Power Down. Setting this bit powers down the AD7763, reducing the power consumption to 6.35 mW.
Low Power. If this bit is set, the AD7763 operates in a low power mode. The power consumption is reduced for a 3 dB
reduction in noise performance.
1 must be written to this bit.
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
0
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
Comment
Download Filter. Before downloading a user-defined filter, this bit must be set. The filter length bits must also
be set at this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until
all the coefficients and the checksum have been written.
Read Overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register
instead of a conversion result.
Read Gain. If this bit is set, the next read operation outputs the contents of the digital gain register.
Read Offset. If this bit is set, the next read operation outputs the contents of the digital offset register.
Read Status. If this bit is set, the next read operation outputs the contents of the status register.
0 must be written to this bit.
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously
on multiple devices synchronizes all filters.
Bypass Filter 3. If this bit is a 0, Filter 3 (programmable FIR) is bypassed.
1 must be written to this bit.
Decimation Rate. These bits set the decimation rate of Filter 2. Writing a value of 0, 1, or 2 corresponds to
4× decimation. A value of 3 corresponds to 8× decimation; a value of 4 corresponds to 16×; and the
maximum value of 5 corresponds to 32× decimation.
0
RD Off
0
RD Stat
0
0
0
SYNC
0
Rev. A | Page 27 of 32
0
FLEN3
0
FLEN2
0
FLEN1
0
PD
FLEN0
BYP F3
LPWR
1
DEC2
1
DEC1
LSB
D1PD
AD7763
LSB
DEC0