AD7730LBRU-REEL7 Analog Devices Inc, AD7730LBRU-REEL7 Datasheet - Page 14

• Manufacturer Part Number: AD7730LBRU-REEL7
• Description: IC ADC TRANSDUCER BRIDGE 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7730LBRU-REEL7

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 600
• Data Interface: DSP, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• For Use With: EVAL-AD7730LEBZ - BOARD EVALUATION FOR AD7730EVAL-AD7730EBZ - BOARD EVAL FOR AD7730

AD7730/AD7730L
Bit
Location
CR3
CR2–CR0
Status Register (RS2–RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex
The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig-
nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7
denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. The number
in brackets indicates the power-on/reset default status of that bit.
Bit
Location
SR7
SR6
SR5
SR4
SR3–SR0
RDY (1)
SR7
Bit
Mnemonic
Bit
Mnemonic
ZERO
RS2–RS0
RDY
STDY
STBY
NOREF
MS3–MS0
STDY (1)
SR6
Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select
These bits are for factory use. The power-on/reset status of these bits vary, depending on the
Description
A zero must be written to this bit to ensure correct operation of the AD7730.
which register type the next read or write operation operates upon as shown in Table VIII.
RS2
0
0
0
0
0
1
1
1
1
Description
Ready Bit. This bit provides the status of the RDY flag from the part. The status and function of
this bit is the same as the RDY output pin. A number of events set the RDY bit high as indi-
cated in Table XVIII.
Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter is
in
remains high as the initial conversion results become available. The RDY output and bit are set
low on these initial conversions to indicate that a result is available. If the STDY is high, however,
it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the
FIR filter has fully settled, the STDY bit will go low coincident with RDY. If the part is never placed
into its
not cleared by subsequent Data Register reads.
A number of events set the STDY bit high as indicated in Table XVIII. STDY is set high along
with RDY by all events in the table except a Data Register read.
Standby Bit. This bit indicates whether the AD7730 is in its Standby Mode or normal mode of
operation. The part can be placed in its standby mode using the STANDBY input pin or by
writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of this bit
is 0 assuming the STANDBY pin is high.
No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.3 V, or
either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on comple-
tion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion
of a calibration, updating of the calibration registers is inhibited.
factory-assigned number.
FASTStep
STBY (0)
SR5
FASTStep
RS1
0
0
0
1
1
0
0
1
1
mode (see Filter Register section) and responding to a step input, the STDY bit
Table IX. Status Register
NOREF (0)
RS0
0
0
1
0
1
0
1
0
1
mode, the STDY bit will go low at the first Data Register read and it is
SR4
Table VIII. Register Selection
–14–
Register
Communications Register (Write Operation)
Status Register (Read Operation)
Data Register
Mode Register
Filter Register
DAC Register
Offset Register
Gain Register
Test Register
MS3 (X)
SR3
MS2 (X)
SR2
MS1 (X)
SR1
MS0 (X)
SR0
REV. A