AD7466BRTZ-R2 Analog Devices Inc, AD7466BRTZ-R2 Datasheet - Page 10

• Manufacturer Part Number: AD7466BRTZ-R2
• Description: IC ADC 12BIT 1.6V LP SOT23-6
• Manufacturer: Analog Devices Inc

Specifications of AD7466BRTZ-R2

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Software Calibrated, 50 MHz to 9 GHz, RF Power Measurement System (CN0178)
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Number Of Converters: 1
• Power Dissipation (max): 900µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Resolution (bits): 12bit
• Sampling Rate: 200kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 1.6V To 3.6V
• Supply Current: 300µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7466CBZ - BOARD EVALUATION FOR AD7466
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7466/AD7467/AD7468
TIMING EXAMPLES
Figure 3 shows some of the timing parameters from Table 4 in
the Timing Specifications section.
Timing Example 1
As shown in Figure 3, f
100 kSPS gives a cycle time of t
Assuming V
4.41 μs = 4.46 μs, and t
which satisfies the requirement of 10 ns for t
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.
SCLK
CS
DD
= 1.8 V, t
POINT A: THE PART IF FULLY POWERED UP WITH V
t
8
2
ACQUISITION TIME
TRACK-AND-HOLD
SCLK
= 60 ns maximum, then t
CONVERT
1
IN TRACK
= 3.4 MHz and a throughput of
CONVERT
= t
2
2
B A
+ 15(1/f
+ t
3
8
+ t
SCLK
QUIET
Figure 3. AD7466 Serial Interface Timing Diagram Example
QUIET
) = 55 ns +
4
QUIET
. The part is
= 10 μs.
2
+ 2(1/f
t
CONVERT
= 5.48 μs,
5
SCLK
IN
Rev. C | Page 10 of 28
FULLY ACQUIRED.
)
1/THROUGHPUT
TRACK-AND-HOLD IN HOLD
13
Timing Example 2
The AD7466 can also operate with slower clock frequencies.
As shown in Figure 3, assuming V
and a throughput of 50 kSPS gives a cycle time of t
t
7.55 μs, and t
μs, which satisfies the requirement of 10 ns for t
fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t
55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of
640 ns for the power-up time. In this example and with other
slower clock values, the part is fully powered up and the signal
already acquired before the third SCLK falling edge; however,
the track-and-hold does not go into hold mode until that point.
In this example, the part can be powered up and the signal can
be fully acquired at approximately Point B in Figure 3.
QUIET
14
= 20 μs. With t
8
15
= 60 ns maximum, this leaves t
t
8
CONVERT
16
= t
POWER-DOWN
AUTOMATIC
2
+ 15(1/f
t
DD
QUIET
= 1.8 V, f
SCLK
) = 55 ns + 7.5 μs =
QUIET
SCLK
QUIET
2
+ 2(1/f
= 2 MHz,
to be 12.39
CONVERT
. The part is
SCLK
+ t
) =
8
+