LTC2215IUP#PBF Linear Technology, LTC2215IUP#PBF Datasheet - Page 27

• Manufacturer Part Number: LTC2215IUP#PBF
• Description: IC ADC 16BIT 65MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2215IUP#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 65M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.25W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF . A resistor in
series with the output may be used, but is not required
since the ADC has a series resistor of 43Ω on-chip.
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 13 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT
vice versa, which creates a ±350mV differential voltage
across the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
APPLICATIONS INFORMATION
LATCH
FROM
LTC2216/LTC2215
DATA
Figure 12. Equivalent Circuit for a Digital Output Buffer
PREDRIVER
LOGIC
DD
V
DD
voltages will also help reduce interference
V
LATCH
LTC2216/LTC2215
DD
FROM
DATA
PREDRIVER
LOGIC
V
OV
DD
Figure 13. Equivalent Output Buffer in LVDS Mode
DD
43Ω
+
to OUT
OV
OGND
DD
10k
TYPICAL
DATA
OUTPUT
1.20V
0.5V
TO 3.6V
0.1μF
22165 F12
–
V
or
DD
+
–
3.5mA
resistor, even if the signal is not used (such as OF
CLKOUT
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output com-
mon mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2216/LTC2215 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3V
An external resistor divider can be user to set the 1/3V
and 2/3V
for the MODE pin.
Table 2. MODE Pin Function
MODE
0V(GND)
1/3V
2/3V
V
DD
10k
DD
DD
OV
DD
+
DD
/CLKOUT
OV
DD
logic levels. Table 2 shows the logic states
43Ω
43Ω
22165 F13
OUTPUT FORMAT
–
2’s Complement
2’s Complement
). To minimize noise the PC board
100Ω
LTC2216/LTC2215
Offset Binary
Offset Binary
OGND
RECEIVER
0.1μF
OV
3.3V
LVDS
DD
DD
, 2/3V
CYCLE STABILIZER
CLOCK DUTY
DD
Off
On
On
Off
and V
+
27
/OF
22165f
–
DD
DD
or
.