MAX113CAG+ Maxim Integrated Products, MAX113CAG+ Datasheet - Page 7

• Manufacturer Part Number: MAX113CAG+
• Description: IC ADC 8BIT 400KSPS 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX113CAG+

• Number Of Bits: 8
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Number Of Converters: 3
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX113/MAX117 use a half-flash conversion tech-
nique (see Functional Diagram ) in which two 4-bit flash
ADC sections achieve an 8-bit result. Using 15 com-
parators, the flash ADC compares the unknown input
voltage to the reference ladder and provides the upper
four data bits. An internal digital-to-analog converter
(DAC) uses the four most significant bits (MSBs) to
generate both the analog result from the first flash con-
version and a residue voltage that is the difference
between the unknown input and the DAC voltage. The
residue is then compared again with the flash com-
parators to obtain the lower four data bits (LSBs).
An internal analog multiplexer enables the devices to
read four (MAX113) or eight (MAX117) different analog
voltages under microprocessor (µP) control. One of the
MAX117’s analog channels, IN8, is internally hard-
wired and always reads V
In burst-mode or low-sample-rate applications, the
MAX113/MAX117 can be shut down between conver-
sions, reducing supply current to microamp levels (see
Typical Operating Characteristics ). A logic low on the
PWRDN pin shuts the devices down, reducing supply
current typically to 1µA when powered from a single
+3V supply. A logic high on PWRDN wakes up the
MAX113/MAX117, and the selected analog input enters
the track mode. The signal is fully acquired after 900ns
(this includes both the power-up delay and the
track/hold acquisition time), and a new conversion can
Figure 1. Load Circuits for Data-Access Time Test
_______________Detailed Description
OUTPUTS
DATA
R
L
= 3k
a) HIGH-Z TO V OH
_______________________________________________________________________________________
C
REF+
L
OUTPUTS
Converter Operation
DATA
when selected.
Power-Down Mode
8-Bit ADCs with 1µA Power-Down
b) HIGH-Z TO V OL
V
DD
R
L
C
= 3k
L
+3V, 400ksps, 4/8-Channel,
be started. If the power-down feature is not required,
connect PWRDN to V
sumption, keep digital inputs at the supply rails in
power-down mode. Refer to the Reference section for
information on reducing the reference current during
power-down.
The MAX113/MAX117 have two basic interface modes,
which are set by the MODE pin. When MODE is low,
the converters are in read mode; when MODE is high,
the converters are set up for write-read mode. The A0,
A1, and A2 inputs control channel selection, as shown
in Table 1. The address must be valid for a minimum
time, t
Figure 2. Load Circuits for Data-Hold Time Test
Table 1. Truth Table for Input Channel
Selection
___________________Digital Interface
OUTPUTS
MAX113
A1
—
—
—
—
DATA
0
0
1
1
3k
ACQ
A0
—
—
—
—
0
1
0
1
, before the next conversion starts.
a) V OH TO HIGH-Z
A2
0
0
0
0
1
1
1
1
MAX117
A1
0
0
1
1
0
0
1
1
DD
A0
0
1
0
1
0
1
0
1
10pF
. For minimum current con-
OUTPUTS
DATA
(reads V
SELECTED CHANNEL
b) V OL TO HIGH-Z
REF+
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
V
DD
if selected)
3k
10pF
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