MAX1081BEUP+ Maxim Integrated Products, MAX1081BEUP+ Datasheet - Page 16

IC ADC 10BIT 300KSPS 20-TSSOP

MAX1081BEUP+

Manufacturer Part Number
MAX1081BEUP+
Description
IC ADC 10BIT 300KSPS 20-TSSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1081BEUP+

Number Of Bits
10
Sampling Rate (per Second)
300k
Data Interface
MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
8.0mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Number Of Adc Inputs
8
Architecture
SAR
Conversion Rate
300 KSPs
Resolution
10 bit
Input Type
Differential
Interface Type
4-Wire (SPI, QSPI, MICROWIRE, TMS320)
Voltage Reference
Internal 2.5 V or External
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Power Dissipation
559 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Figure 7. Detailed Serial-Interface Timing
Table 4. Software-Controlled Power Modes
*Circuit operation between conversions; during conversion all circuits are fully powered up.
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer-
ence, the MAX1080/MAX1081 can be considered fully
powered up within 2µs of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time is dependent on the external bypass
capacitors and shutdown duration.
The MAX1080/MAX1081 automatic power-down modes
can save considerable power when operating at less
than maximum sample rates. Figures 10 and 11 show
16
PD1/PD0
______________________________________________________________________________________
00
01
10
11
SSTRB
DOUT
SCLK
DIN
CS
Full Power-Down
(FULLPD)
Fast Power-Down
(FASTPD)
Reduced-Power
Mode (REDP)
Normal Operating
t
t
DOE
STE
t
CSO
MODE
Power-Down Sequencing
t
CSS
t
Hardware Power-Down
DS
t
DH
t
CL
CONVERTING
TOTAL SUPPLY CURRENT
(mA)
t
CH
2.5
2.5
2.5
2.5
CONVERSION
AFTER
0.9mA
1.3mA
2.0mA
2µA
the average supply current as a function of the sam-
pling rate.
Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per chan-
nel per second. Figure 10a shows the MAX1081’s
power consumption for one- or eight-channel conver-
sions utilizing full power-down mode (PD1 = PD0 = 0),
with the internal reference and the maximum clock
speed. A 0.01µF bypass capacitor at REFADJ forms an
RC filter with the internal 17kΩ reference resistor, with a
200µs time constant. To achieve full 10-bit accuracy,
seven time constants or 1.4ms are required after
power-up if the bypass capacitor is fully discharged
between conversions. Waiting this 1.4ms duration in
t
CP
t
t
DOH
DOV
t
STH
t
STV
INPUT COMPARATOR
Reduced Power
Reduced Power
Full Power
t
CSH
Off
CIRCUIT SECTIONS*
Using Full Power-Down Mode
t
CSW
t
t
t
CS1
DOD
STD
REFERENCE
Off
On
On
On

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