MAX1241BCSA+ Maxim Integrated Products, MAX1241BCSA+ Datasheet - Page 4

• Manufacturer Part Number: MAX1241BCSA+
• Description: IC ADC SERIAL 12BIT 2.7V 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX1241BCSA+

• Number Of Bits: 12
• Sampling Rate (per Second): 73k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 471mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Adc Inputs: 1
• Architecture: SAR
• Conversion Rate: 73 KSPs
• Resolution: 12 bit
• Input Type: Voltage
• Voltage Reference: External
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
capacitor at REF pin, MAX1241—external reference; V
TIMING CHARACTERISTICS (Figure 8)
(V
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: MAX1240—internal reference, offset nulled; MAX1241—external reference (V
Note 4: External load should not change during conversion for specified accuracy.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Measured as [V
Note 7: To guarantee acquisition time, t
4
POWER REQUIREMENTS
Supply Voltage
Supply Current
Supply Rejection
Acquisition Time
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Low to CS Fall Setup Time
DOUT Rise to SCLK Rise (Note 5)
CS Pulse Width
DD
DD
_______________________________________________________________________________________
= +2.7V to +3.6V (MAX1240); V
= +2.7V to +3.6V (MAX1240); V
offset have been calibrated.
time needed for the signal to be acquired.
PARAMETERS
PARAMETERS
DD
= +2.7V.
FS
(2.7V) - V
SYMBOL
SYMBOL
FS
DD
DD
f
t
(V
V
PSR
SCLK
t
t
I
ACQ
t
t
t
t
t
t
CS0
STR
DD
DO
CH
DV
CL
CS
TR
DD
ACQ
= +2.7V to +5.25V (MAX1241); T
DD(MAX
= +2.7V to +5.25V (MAX1241); 73ksps, f
is the maximum time the device takes to acquire the signal, and is also the minimum
MAX1240
MAX1241
Operating
mode
Power-down, digital inputs
at 0V or V
(Note 5)
CS = V
Figure 1,
C
Figure 1, C
Figure 2, C
)].
LOAD
REF
DD
= 50pF
DD
(Note 6)
= 2.500V applied to REF pin; T
LOAD
LOAD
MAX1240A/B
MAX1240C
MAX1241A/B
MAX1241C
CONDITIONS
CONDITIONS
= 50pF
= 50pF
MAX124_ _C/E
MAX124_ _M
A
= T
V
V
V
V
V
V
V
V
MIN
DD
DD
DD
DD
DD
DD
DD
DD
SCLK
= 3.6V
= 3.6V
= 3.6V
= 5.25V
= 3.6V
= 5.25V
= 3.6V
= 5.25V
to T
REF
MAX
= 2.1MHz (50% duty cycle); MAX1240—4.7µF
A
= +2.500V), offset nulled.
, unless otherwise noted.)
= T
MIN
to T
MIN
MIN
200
200
240
2.7
2.7
1.5
20
20
50
0
0
MAX
; unless otherwise noted.)
TYP
±0.3
TYP
1.4
1.4
0.9
1.6
0.9
1.6
1.9
3.5
MAX
MAX
5.25
200
240
240
240
3.6
2.0
3.5
1.5
2.5
2.8
3.8
2.1
10
15
UNITS
UNITS
MHz
mA
mV
µA
µs
ns
ns
ns
ns
ns
ns
ns
ns
V