AD9875BST Analog Devices Inc, AD9875BST Datasheet - Page 20

• Manufacturer Part Number: AD9875BST
• Description: IC 10BIT MODEM MXFE 48-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9875BST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 10
• Number Of Channels: 1
• Power (watts): 950mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 48-LQFP
• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

AD9875
increment the address for each successive byte required for the
multibyte communication cycle. Figures 10a and 10b show how
the serial port words are built for each of these modes.
Address
(hex)
0
1
2
3
4
5
6
7
8
F
SENABLE
SENABLE
Figure 10a. Serial Register Interface Timing MSB-First
Figure 10b. Serial Register Interface Timing LSB-First
SDATA
SDATA
SCLK
SCLK
Bit 7
Power-Down
Regulator
Power-Down
Regulator
Tx Port
Negative
Edge Sampling PLL-B/2
Rx LPF
Tuning Update Tuning
Disable
Invert
CLK B
R/W I6
I0
I1
(N)
INSTRUCTION CYCLE
INSTRUCTION CYCLE
I5
I2
(N)
I4
I3
I3
I4
Bit 6
SPI
LSB First
Power-
Down
PLL-B
Power-
Down
PLL-B
ADC Clock
Source
Rx LPF
In Progress
(Read Only)
Interpolation Filter Select
<3:0>
Invert
CLK A
I5
I2
(N)
I6
I1
(N)
R/W
I0
D7
D0
Bit 5
Software
Reset
Power-
Down
PLL-A
Power-
Down
PLL-A
Rx Path
DC Offset HPF
Correction Bypass
PGA
Gain Set
by Register
Disable
CLK B
N
0
D6
D1
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
N
0
D2
(×M) Multiplier
< 5:4>
PLL-B
Rx LPF Fc Adjust <7:0>
0
Bit 4
Power-
Down
DAC
Power-
Down
DAC
Rx Digital Fast ADC
Disable
CLK A
D2
0
Table IV. Register Layout
D1
D6
0
N
D7
D0
N
0
Bit 3
Power-Down Power-
Interpolator
Power-
Down
Interpolator
Sampling
Power-Down Tx Port
Interpolator
at Tx QUIET First
Pin Low
Three-State
Rx Port
Rx Path Gain Adjust <4:0>
–20–
Die Revision Number <3:0>
PLL-B
( ) Divider
< 3:2>
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all registers
except register 0 are set to their default values. Register 0 will
remain at the last value sent, with the exception that the Software
Reset bit will be set to 0.
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK,
a byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9875 are not simultaneously
updated, but occur sequentially. For this reason, it is recom-
mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
Bit 2
Down Rx
Reference
Power-
Down Rx
Reference
Wideband
Rx LPF
LS Nibble
Rx Port
LS Nibble
First
Bit 1
Power-
Down ADC Down Rx
and FPGA
Power-
Down ADC Down Rx
and FPGA
Enable
1-Pole
Rx LPF
Tx Port
Width
5-bits
Rx Port
Width
5-bits
PLL-A
(×L) Multiplier
< 1:0>
LPF and
LPF and
Bit 0
Power-
CPGA
Power-
CPGA
Rx LPF
Bypass
Tx Port
Multiplexer
Bypass
Rx Port
Multiplexer
Bypass
Default
(hex)
0 × 00
0 × 00
0 × 9F
0 × 02
0 × 01
0 × 80
0 × 00
0 × 00
0 × 00
Comments
Read/Write
Read/Write
PWR DN
Pin Low
Read/Write
PWR DN
Pin High
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/ Write
Read Only
REV. A